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Change subject: soc/mediatek/mt8196: Add MMinfra driver support
......................................................................
Patch Set 5:
(1 comment)
File src/soc/mediatek/mt8196/mminfra_pd.c:
https://review.coreboot.org/c/coreboot/+/85188/comment/67ec4176_f97dbc32?us… :
PS5, Line 35: while (read32p(MMINFRA_MM0_GALS_PROT_TX_RDY) != 0xff)
: ;
> Should we want potential endless loops? Maybe add some timeout?
Since this is a very basic MM register setting, if the while loop gets stuck, it indicates some hardware issues. Continuing execution might lead to unexpected behavior.
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Change subject: nb/via/cx700/romstage: Include missing static.h header
......................................................................
Patch Set 1: Code-Review+2
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Change subject: nb/via/cx700/romstage: Include missing static.h header
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Patch Set 1: Code-Review+2
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Change subject: nb/via/cx700/romstage: Include missing static.h header
......................................................................
nb/via/cx700/romstage: Include missing static.h header
Commit 755ecc259c42 ("nb/via/cx700: Implement raminit") is missing an
include for static.h and breaks the main branch. Fix it.
Change-Id: I836ab03b4eba6f32a2ae576eafc465543179cd05
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/northbridge/via/cx700/romstage.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85232/1
diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c
index b73dd91..d554b76 100644
--- a/src/northbridge/via/cx700/romstage.c
+++ b/src/northbridge/via/cx700/romstage.c
@@ -8,6 +8,7 @@
#include <static_devices.h>
#include <arch/romstage.h>
#include <cbmem.h>
+#include <static.h>
#include "chip.h"
#include "raminit.h"
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Change subject: mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/trulo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/85184/comment/6217104d_f2dee8e9?us… :
PS4, Line 184: register "power_limits_config[ADL_N_041_6W_CORE]" = "{
: .tdp_pl1_override = 20,
: .tdp_pl2_override = 25,
: .tdp_pl4 = 78,
: }"
:
: register "power_limits_config[ADL_N_081_7W_CORE]" = "{
: .tdp_pl1_override = 20,
: .tdp_pl2_override = 25,
: .tdp_pl4 = 78,
: }"
:
: register "power_limits_config[ADL_N_081_15W_CORE]" = "{
: .tdp_pl1_override = 20,
: .tdp_pl2_override = 35,
: .tdp_pl4 = 83,
: }"
> PL1/PL2 override hooks can still be used by ODMs by adding this block of code back. But overriding PL1/PL2 to a higher value as done here should not be a default guidance given from a reference design as using a higher PLx can have thermal impacts to silicon. This code block seems to be copied from some other production device variant that is also using a higher override for PLx values. Such overrides are not part of any other reference design variant.
This code may coexist with the actual limit if there's a check to assert the build if the overridden value is larger than the limit. Ideally, a check like this should be included.
There is no override required if overriden value is invalid or matches to the existing limit.
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