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Change subject: stddef.h: Introduce nullptr constant
......................................................................
Patch Set 26:
(1 comment)
File src/include/stddef.h:
https://review.coreboot.org/c/coreboot/+/83459/comment/d4972a81_706e3a95?us… :
PS26, Line 25: #define nullptr ((void *)0)
> I don't remember exactly what was said but I agree with Felix here: I think the important part is th […]
To be clear, my concern is only about the `#define nullptr` on the old path, not the C23 path.
As Julius suggests this may help with imported code, but that means we'd have to
weigh if it's more likely to be code that expects `nullptr` to be provided by
`stddef.h` (why would it be? it's not in any standard AFAIK) or code that may
even have a completely different use for this identifier. Seems rather undecidable
to me, so I'd suggest to do less and deal with imported code when it comes.
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Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/79404?usp=email )
Change subject: acpi: Add IORT helper functions
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79404/comment/1c26355a_be08759c?us… :
PS8, Line 13: ITS(Interrupt Translation Service)
> Please add a space before the (.
Acknowledged
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84161?usp=email )
Change subject: tree: Use boolean for dptf_enable
......................................................................
tree: Use boolean for dptf_enable
Change-Id: Ic6e578199e7e4ca3a014eecb1eb7a4d9d24893b8
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84161
Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/tigerlake/chip.h
2 files changed, 2 insertions(+), 2 deletions(-)
Approvals:
Frans Hendriks: Looks good to me, approved
build bot (Jenkins): Verified
Erik van den Bogaert: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index e3a23b2..061621c 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -130,7 +130,7 @@
/* Enable S0iX support */
bool s0ix_enable;
/* Enable DPTF support */
- int dptf_enable;
+ bool dptf_enable;
/* Deep SX enable for both AC and DC */
int deep_s3_enable_ac;
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 630317a..f0cecb3 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -149,7 +149,7 @@
uint8_t TcssD3HotDisable;
/* Enable DPTF support */
- int dptf_enable;
+ bool dptf_enable;
/* Deep SX enable for both AC and DC */
int deep_s3_enable_ac;
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Leo Chou has uploaded a new patch set (#3) to the change originally created by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/84573?usp=email )
Change subject: mb/google/nissa/var/pujjoga: Change configure_ext_fivr value
......................................................................
mb/google/nissa/var/pujjoga: Change configure_ext_fivr value
Change configure_ext_fivr value of register ext_fivr_settings
to zero to resolve black screen issue.
BUG=b:354759177
Test=emerge-nissa coreboot
Change-Id: Idb51a431ba6c6089d5c9d29adad9ab2a67979447
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---
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Change subject: mb/google/nissa/var/pujjoga: Change configure_ext_fivr value
......................................................................
mb/google/nissa/var/pujjoga: Change configure_ext_fivr value
Change configure_ext_fivr value of register ext_fivr_settings to zero to resolve black screen issue.
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I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/cezanne: Heal the corruption in A/B recovery
......................................................................
soc/amd/cezanne: Heal the corruption in A/B recovery
Change-Id: I2cdab00a7122e4831fe5d91cf5d390ad11db0999
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/soc/amd/cezanne/Makefile.mk
A src/soc/amd/cezanne/abrecovery.c
M src/soc/amd/cezanne/include/soc/cpu.h
3 files changed, 228 insertions(+), 0 deletions(-)
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Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84264?usp=email )
Change subject: mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84264/comment/b831ae64_47d4a776?us… :
PS1, Line 8:
> Is this ordering consistent with other devicetree files?
There doesn't seem to be a common way
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Change subject: mb/starlabs/starbook/cml: Alphabetize and group FSP UPDs
......................................................................
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(1 comment)
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PS1, Line 8:
Is this ordering consistent with other devicetree files?
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Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/starlabs/starbook/cml: Remove PMC GPIO routing
......................................................................
mb/starlabs/starbook/cml: Remove PMC GPIO routing
These aren't used so remove them.
Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
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