coreboot-gerrit October 2024

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[M] Change in coreboot[main]: soc/intel/adl to jsl: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 01 Oct '24

01 Oct '24

1 0

[S] Change in coreboot[main]: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Shuo Liu, Subrata Banik, Tarun, Tim Chu. Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84609?usp=email ) Change subject: soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc ...................................................................... soc/intel/mtl to xeon_sp: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/soc/intel/meteorlake/acpi.c M src/soc/intel/meteorlake/chip.c M src/soc/intel/meteorlake/cpu.c M src/soc/intel/meteorlake/espi.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/pmc.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/meteorlake/systemagent.c M src/soc/intel/meteorlake/tcss.c M src/soc/intel/pantherlake/acpi.c M src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/cpu.c M src/soc/intel/pantherlake/espi.c M src/soc/intel/pantherlake/pmc.c M src/soc/intel/pantherlake/pmutil.c M src/soc/intel/pantherlake/romstage/fsp_params.c M src/soc/intel/pantherlake/systemagent.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/fadt.c M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/romstage/fsp_params.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/tigerlake/bootblock/pch.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/pmc.c M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/tigerlake/romstage/fsp_params.c M src/soc/intel/tigerlake/systemagent.c M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lpc.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 43 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/84609/1 diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index a3ee198..e3aa44e 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -20,6 +20,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 84b9235b2..4f304dc 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -24,6 +24,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/meteorlake/cpu.c b/src/soc/intel/meteorlake/cpu.c index e990ae3..4a74be0 100644 --- a/src/soc/intel/meteorlake/cpu.c +++ b/src/soc/intel/meteorlake/cpu.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> bool cpu_soc_is_in_untrusted_mode(void) { diff --git a/src/soc/intel/meteorlake/espi.c b/src/soc/intel/meteorlake/espi.c index a3952a3..98fd9fc 100644 --- a/src/soc/intel/meteorlake/espi.c +++ b/src/soc/intel/meteorlake/espi.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> +#include <static.h> void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index bf1d9d5..7d4d504 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -31,6 +31,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> #include <stdlib.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c index 5c4fa2c..837a8f3 100644 --- a/src/soc/intel/meteorlake/pmc.c +++ b/src/soc/intel/meteorlake/pmc.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #include <bootstate.h> diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 09fb46b..8e91b27 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 917503e..bc7c20b 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -26,6 +26,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> #include <string.h> #include <ux_locales.h> diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 774a99f..bb841aa 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * SoC implementation diff --git a/src/soc/intel/meteorlake/tcss.c b/src/soc/intel/meteorlake/tcss.c index 7509504..3d46f0a 100644 --- a/src/soc/intel/meteorlake/tcss.c +++ b/src/soc/intel/meteorlake/tcss.c @@ -2,6 +2,7 @@ #include <intelblocks/tcss.h> #include <soc/soc_chip.h> +#include <static.h> const struct soc_tcss_ops tcss_ops = { .configure_aux_bias_pads = ioe_tcss_configure_aux_bias_pads_sbi, diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index fd17ef5..05479ef 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -20,6 +20,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 4e7d573..9e25db4 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -24,6 +24,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 7856383..422efb2 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/soc_chip.h> #include <soc/soc_info.h> +#include <static.h> bool cpu_soc_is_in_untrusted_mode(void) { diff --git a/src/soc/intel/pantherlake/espi.c b/src/soc/intel/pantherlake/espi.c index 02bec6f..d5b5cf9 100644 --- a/src/soc/intel/pantherlake/espi.c +++ b/src/soc/intel/pantherlake/espi.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> +#include <static.h> void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { diff --git a/src/soc/intel/pantherlake/pmc.c b/src/soc/intel/pantherlake/pmc.c index 1c1ca5d..de6bf0c 100644 --- a/src/soc/intel/pantherlake/pmc.c +++ b/src/soc/intel/pantherlake/pmc.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <stdint.h> #define PMC_HID "INTC1026" diff --git a/src/soc/intel/pantherlake/pmutil.c b/src/soc/intel/pantherlake/pmutil.c index 892972c..888bb56 100644 --- a/src/soc/intel/pantherlake/pmutil.c +++ b/src/soc/intel/pantherlake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> /* diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 4d5e178..0a17756 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -10,6 +10,7 @@ #include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_info.h> +#include <static.h> #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index 418f41c..e7a0701 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * SoC implementation diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e0381e8..3a60ada 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -17,6 +17,7 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index cc2d384..df00bb8 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/pmc.h> +#include <static.h> #include "../chip.h" #define PCR_DMI_ACPIBA 0x27B4 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index d1cc6f9..a6844e0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -28,6 +28,7 @@ #include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/usb.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 5cf48ea..afe1c24 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -21,6 +21,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/skylake/fadt.c b/src/soc/intel/skylake/fadt.c index 693218f..5de44d3 100644 --- a/src/soc/intel/skylake/fadt.c +++ b/src/soc/intel/skylake/fadt.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <static.h> #include "chip.h" void soc_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index eea86fc..4b957df 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -10,6 +10,7 @@ #include <soc/iomap.h> #include <soc/pcr_ids.h> #include <soc/intel/common/block/lpc/lpc_def.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 71d1ef0..7c8d7c1 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -11,6 +11,7 @@ #include <intelblocks/rtc.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 5152237..5e7d543 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -24,6 +24,7 @@ #include <soc/pmc.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index f24054a..bd3d086 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -10,6 +10,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <static.h> static void cpu_flex_override(FSP_M_CONFIG *m_cfg) { diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index d203bda..3708f05 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -12,6 +12,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <static.h> #include <types.h> #include "chip.h" diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index c34b185..dd9ef73 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -19,6 +19,7 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * List of supported C-states in this processor. diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 64e8b2e..084bd7f 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -27,6 +27,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> +#include <static.h> #if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1000 diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index f90f8ad..f2ccb48 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <static.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 3d0f0e9..0c6f36e 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -20,6 +20,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> +#include <static.h> #include <types.h> bool cpu_soc_is_in_untrusted_mode(void) diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 6ef7c6d..3b56e29 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> +#include <static.h> void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) { diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index d5472dd..7c35b7a 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -26,6 +26,7 @@ #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <soc/tcss.h> +#include <static.h> #include <string.h> #include <types.h> diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 0bba1a0..8912cb3 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -20,6 +20,7 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> +#include <static.h> #include <bootstate.h> #define PMC_HID "INTC1026" diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index ba33e49..cd22942 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -30,6 +30,7 @@ #include <soc/smbus.h> #include <soc/soc_chip.h> #include <security/vboot/vbnv.h> +#include <static.h> /* * SMI diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 00b5315..5ebd46d 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -16,6 +16,7 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <static.h> #include <string.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c index 06282ea..143fd72 100644 --- a/src/soc/intel/tigerlake/systemagent.c +++ b/src/soc/intel/tigerlake/systemagent.c @@ -17,6 +17,7 @@ #include <soc/iomap.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> +#include <static.h> /* * SoC implementation diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index e0c2f3b..b6b8e00 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -8,6 +8,7 @@ #include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/util.h> +#include <static.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 2a85032..ffcb052 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -13,6 +13,7 @@ #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> #include <soc/soc_util.h> +#include <static.h> #include <string.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 7b46564..95ad608 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -4,6 +4,7 @@ #include <intelblocks/lpc_lib.h> #include <soc/iomap.h> #include <soc/pcr_ids.h> +#include <static.h> #include <chip.h> diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 4a8c6b0..21b3522 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -4,6 +4,7 @@ #include <intelblocks/rtc.h> #include <soc/romstage.h> #include <soc/soc_util.h> +#include <static.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index b05c7e7..4762231 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -18,6 +18,7 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/soc_pch.h> +#include <static.h> #include <string.h> #include <soc/config.h> #include <soc/soc_util.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/84609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c118a707dfe7bb8932606f30eae52ef0b4c9efe Gerrit-Change-Number: 84609 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: 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[S] Change in coreboot[main]: soc/amd/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84587?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/*: Explicitly include static.h for config_of_soc ...................................................................... soc/amd/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/soc/amd/cezanne/acpi.c M src/soc/amd/cezanne/config.c M src/soc/amd/cezanne/fch.c M src/soc/amd/cezanne/fsp_m_params.c M src/soc/amd/cezanne/i2c.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/genoa_poc/config.c M src/soc/amd/genoa_poc/i2c.c M src/soc/amd/glinda/acpi.c M src/soc/amd/glinda/config.c M src/soc/amd/glinda/fch.c M src/soc/amd/glinda/fsp_m_params.c M src/soc/amd/glinda/i2c.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/mendocino/config.c M src/soc/amd/mendocino/fch.c M src/soc/amd/mendocino/fsp_m_params.c M src/soc/amd/mendocino/i2c.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/phoenix/config.c M src/soc/amd/phoenix/fch.c M src/soc/amd/phoenix/fsp_m_params.c M src/soc/amd/phoenix/i2c.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/config.c M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/fsp_m_params.c M src/soc/amd/picasso/fsp_s_params.c M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/stoneyridge/i2c.c 33 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/84587/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9db5d80ca0a75ccff3b8e24db0ccbd6b36c84dcb Gerrit-Change-Number: 84587 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: tree: Explicitly include static.h for referencing static devices
by Nicholas Chin (Code Review) 01 Oct '24

01 Oct '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84591?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: tree: Explicitly include static.h for referencing static devices ...................................................................... tree: Explicitly include static.h for referencing static devices As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Add static.h to the includes of files that directly access the static __pci_* devices from static_devices.h. Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/northbridge/intel/gm45/northbridge.c M src/soc/intel/common/block/systemagent/systemagent.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/84591/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d35ff2ac22f9ff5e0aa38b7ad707619e50387f3 Gerrit-Change-Number: 84591 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/*: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Eric Lai, Felix Held, Fred Reitberger, Jakub Czapiga, Jason Glenesk, Jason Nien, Jayvik Desai, Johnny Lin, Kapil Porwal, Martin Roth, Nick Vaccaro, Patrick Rudolph, Sean Rhodes, Subrata Banik, Tarun, Tim Chu. Hello Angel Pons, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Patrick Rudolph, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84588?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/*: Explicitly include static.h for config_of_soc ...................................................................... mb/*: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/mainboard/amd/bilby/mainboard.c M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c M src/mainboard/amd/mandolin/mainboard.c M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c M src/mainboard/google/dedede/mainboard.c M src/mainboard/google/dedede/variants/awasuki/ramstage.c M src/mainboard/google/dedede/variants/baseboard/ramstage.c M src/mainboard/google/dedede/variants/drawcia/ramstage.c M src/mainboard/google/dedede/variants/kracko/ramstage.c M src/mainboard/google/dedede/variants/lantis/ramstage.c M src/mainboard/google/dedede/variants/pirika/ramstage.c M src/mainboard/google/dedede/variants/sasukette/ramstage.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/hatch/variants/akemi/variant.c M src/mainboard/google/hatch/variants/kindred/variant.c M src/mainboard/google/poppy/variants/atlas/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/nocturne/mainboard.c M src/mainboard/google/puff/variants/baseboard/mainboard.c M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c M src/mainboard/google/rex/variants/deku/ramstage.c M src/mainboard/google/zork/variants/baseboard/ramstage_common.c M src/mainboard/google/zork/variants/dalboz/variant.c M src/mainboard/google/zork/variants/shuboz/variant.c M src/mainboard/google/zork/variants/vilboz/variant.c M src/mainboard/intel/adlrvp/ramstage.c M src/mainboard/intel/avenuecity_crb/romstage.c M src/mainboard/intel/beechnutcity_crb/romstage.c M src/mainboard/lattepanda/mu/ramstage.c M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c M src/mainboard/starlabs/lite/devtree.c M src/mainboard/starlabs/starbook/variants/adl/devtree.c M src/mainboard/starlabs/starbook/variants/cml/devtree.c M src/mainboard/starlabs/starbook/variants/kbl/devtree.c M src/mainboard/starlabs/starbook/variants/rpl/devtree.c M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 43 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/84588/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84588?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4 Gerrit-Change-Number: 84588 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> 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<jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/intel/adl to jsl: Explicitly include static.h for config_of_soc
by Nicholas Chin (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Werner Zeh. Hello Arthur Heymans, Christian Walter, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Pranava Y N, Sean Rhodes, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84586?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/adl to jsl: Explicitly include static.h for config_of_soc ...................................................................... soc/intel/adl to jsl: Explicitly include static.h for config_of_soc As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/espi.c M src/soc/intel/alderlake/finalize.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/pmc.c M src/soc/intel/alderlake/pmutil.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/graphics.c M src/soc/intel/alderlake/systemagent.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/pnpconfig.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/gpio_common.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/systemagent.c M src/soc/intel/cannonlake/vr_config.c M src/soc/intel/common/block/chip/chip.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/power_limit/power_limit.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/pmc.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/elkhartlake/romstage/fsp_params.c M src/soc/intel/elkhartlake/systemagent.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/jasperlake/systemagent.c M src/soc/intel/jasperlake/xhci.c 52 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/84586/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03e42689487c6d63436d9c2945558073aae87cd1 Gerrit-Change-Number: 84586 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: libpayload: Remove default empty implementations in mock cache.h
by Hsuan-ting Chen (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Yu-Ping Wu. Hsuan-ting Chen has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84608?usp=email ) Change subject: libpayload: Remove default empty implementations in mock cache.h ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4383bf95435fd7d74d624b19b79b5a117cf6d00 Gerrit-Change-Number: 84608 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Oct 2024 02:45:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads
by Ren Kuo (Code Review) 01 Oct '24

01 Oct '24

Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/84545?usp=email ) Change subject: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84545/comment/7eecc5a4_7f4f2e87?us… : PS4, Line 8: : In previous cl:84124 > Previously in CB:84124 fixed. https://review.coreboot.org/c/coreboot/+/84545/comment/066dd6fc_3ecaa5a1?us… : PS4, Line 10: , and fp_disable_pads need to be updated. > . Hence update fp_disable_pads configuration to include that GPIO. fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/84545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Gerrit-Change-Number: 84545 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Oct 2024 02:43:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads
by Ren Kuo (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Ren Kuo. Hello Karthik Ramasubramanian, Kenneth Chan, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84545?usp=email to look at the new patch set (#5). Change subject: mb/google/brox/jubilant: Modify FP IRQ pin on disable pads ...................................................................... mb/google/brox/jubilant: Modify FP IRQ pin on disable pads In previous CB:84124, FP IRQ pin has been changed to GPP_D13 from GPP_F15. Hence update fp_disable_pads configuration to include that GPIO. BUG=None TEST= build firmware $ emerge-brox coreboot Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/fw_config.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/84545/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Gerrit-Change-Number: 84545 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Delete duplicated line
by Subrata Banik (Code Review) 01 Oct '24

01 Oct '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84607?usp=email ) Change subject: soc/intel/pantherlake: Delete duplicated line ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea26d962748116fa84afdb4afcba1098a64b6987 Gerrit-Change-Number: 84607 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 01 Oct 2024 01:34:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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