coreboot-gerrit January 2024

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[L] Change in coreboot[main]: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
by Mike Banon (Code Review) 07 Jan '24

07 Jan '24

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79838?usp=email ) Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards ...................................................................... util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards restore_agesa.sh reverts the opensource AGESA AMD boards removal that happened after 5e8e911b7caee021faff96c4e82a77a42544ea62 commit (0 point of history, or 0 PoH) - by git-reverting: 1) the "bad commits" (marked as "CBF" = coreboot build failure) - that either remove or break a code needed for our boards 2) the "unlucky commits" (marked as "GRF" = git revert failure) - that are a roadblock for git-reverting the "bad commits" Right now at 8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 (5464 PoH), it takes 44 CBF git reverts - just 1% of 5464 commits since the OSS AGESA removal! - making this removal look questionable and the idea of opensource AGESA AMD boards restoration viable. SUCCESSFUL BOOT TESTS for the opensource AGESA boards which I own (Lenovo G505S - fam15 laptop, ASUS A88XM-E - fam15 desktop, ASUS AM1I-A - fam16 desktop) : 8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 (5464 PoH) for Lenovo G505S 69ffebf5ccf123bc0b3fb28b485985af0597761d (3698 PoH) for ASUS A88XM-E Change-Id: Ia97e80ffaad9459e54ff5cb01f20d9129241433c Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- A util/scripts/restore_agesa.sh 1 file changed, 263 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/79838/1 diff --git a/util/scripts/restore_agesa.sh b/util/scripts/restore_agesa.sh new file mode 100755 index 0000000..bc6d7cb --- /dev/null +++ b/util/scripts/restore_agesa.sh @@ -0,0 +1,263 @@ +#!/usr/bin/env sh +# +# restore_agesa.sh reverts the opensource AGESA AMD boards removal +# that happened after 5e8e911b7caee021faff96c4e82a77a42544ea62 +# commit (0 point of history, or 0 PoH) - by git-reverting: +# 1) the "bad commits" (marked as "CBF" = coreboot build failure) +# - that either remove or break a code needed for our boards +# 2) the "unlucky commits" (marked as "GRF" = git revert failure) +# - that are a roadblock for git-reverting the "bad commits" +# +# Right now at 8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 (5464 PoH), +# it takes 44 CBF git reverts - just 1% of 5464 commits since the +# OSS AGESA removal! - making this removal look questionable and +# the idea of opensource AGESA AMD boards restoration viable. +# +# SUCCESSFUL BOOT TESTS for the opensource AGESA boards which I own +# (Lenovo G505S - fam15 laptop, ASUS A88XM-E - fam15 desktop, +# ASUS AM1I-A - fam16 desktop) : +# 8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 (5464 PoH) for Lenovo G505S +# 69ffebf5ccf123bc0b3fb28b485985af0597761d (3698 PoH) for ASUS A88XM-E +# +# Copyright (C) 2024 Mike Banon <mikebdp2(a)gmail.com> +# SPDX-License-Identifier: GPL-3.0-or-later +# + +git reset --hard 8b89f89ecb7bb4c029d34eee2b48418336aa7ac1 # 5464 ####### - this is a coreboot master at the moment + +git revert --no-edit ba07f95992d4a430383696a4654ad222178df242 # 5399 # CBF # soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42 +git revert --no-edit ba757a71fef07d876f06a35b6374bcf00f40ded6 # 5398 # GRF # x86: Separate CPU and SoC physical address size +git revert --no-edit 1cf942c18f893f9a2bb6eadbfb867b8ad0e68dbd # 5397 # GRF # Revert "cpu/intel/common: Define build time physical address reserved bits" +git revert --no-edit 9bcbdbf9e48f3977cf5d48732527bbf02fea02de # 5381 # CBF # nb,sb/amd/pi/*/pci_devs: drop unused PCI device IDs +git revert --no-edit 0f98655b37d32f0a8c7f778e2683ea6c595ee88d # 5361 # CBF # device: Drop MULTIPLE_VGA_ADAPTERS Kconfig +git revert --no-edit df4955297f8fd798c1faf61cf92577edd4b2a7ce # 5360 # CBF # nb/amd/pi: drop HW_MEM_HOLE_SIZEK Kconfig option +git revert --no-edit 3f234f85e2cb069e7de75c9d6259934e7916fe87 # 5358 # GRF # nb/amd/pi/00730F01/northbridge: assume that there's DRAM +git revert --no-edit dda7793e53f514c7502c0b51e350eb8730a357b8 # 5350 # GRF # nb/amd/pi/00730F01: assign IOMMU ops in chipset devicetree +git revert --no-edit 7b9c6472179dc7a688c7728e4371d0cde0e7791a # 5349 # GRF # nb/amd/pi/00730F01: assign northbridge ops in chipset devicetree +git revert --no-edit 9314bb6f0a991593b5fb9a6a6cced5aad02e6587 # 5331 # GRF # vc/amd/opensil: add _POC suffix to SOC_AMD_OPENSIL_GENOA +git revert --no-edit d123f8d8716811149ecdf7d51661d8cee6f48577 # 5330 # GRF # soc/amd/genoa: rename to genoa_poc +git revert --no-edit 017003cbd0b75119cd1ee6ff52236f8a18182c3c # 5325 # GRF # acpi: Add support for WDAT table +git revert --no-edit c7be0781ce0849a54ee75ffb30dd3c0a3716cca3 # 5320 # GRF # vc/amd: use 'openSIL' spelling in comments & help text +git revert --no-edit b15494900479bf2d4260c8b6696ece6bcc631102 # 5319 # GRF # soc/amd: drop fill_fadt_extended_pm_regs +git revert --no-edit 3d3e1cf060ccf5701e2ccb0a1698fa804badef90 # 5305 # GRF # vendorcode/amd/opensil/genoa_poc: add opensil_fill_fadt_io_ports +git revert --no-edit 5f6cf6105c701f017c1a194710b05bba2756d003 # 5286 # GRF # vendorcode/amd/genoa: Parse APOB for DRAM layout +git revert --no-edit f1b1412068684e2e1973b594cb6f6b2026db4fb5 # 5284 # GRF # soc/amd/genoa: Add opensil MPIO chip files +git revert --no-edit 62389ab04a4ea90a3246465ce28d18fa3950149a # 5283 # GRF # vendorcode/amd/opensil: Add SATA configuration +git revert --no-edit f643a4d77eec14a617e0b75e58a18aec3ebf7686 # 5281 # GRF # vendorcode/amd/opensil: Add USB configuration +git revert --no-edit e46af3fca48f0d624d1380bca1e40741cb2c1caa # 5267 # GRF # soc/intel/cse: Add API to check if CSE Firmware update is required +git revert --no-edit 81ceea1592a5b806c5d892fbf51b5655d78fe135 # 5259 # GRF # vendorcode/amd/opensil: Set up resource manager input block +git revert --no-edit 4a9ed707c80543f4dd4a586f2d4131e3d4f468e7 # 5252 # GRF # acpi: add missing device/device.h include +git revert --no-edit adee6a694509d61fef01a4a885842299f89b40e0 # 5246 # GRF # vendorcode/amd/opensil: Add initial setup and API calls +git revert --no-edit 903454e7b865b5b3d3a1615372d6eb5974ef4435 # 5244 # GRF # sb/intel/bd82x6x: assign EHCI controller ops in chipset devicetree +git revert --no-edit afebab1ebe109c7b9ca9820679a4681b996bce0b # 5243 # GRF # sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree +git revert --no-edit 898757fc44e73654c8c093a754356820ea42a355 # 5242 # GRF # sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree +git revert --no-edit 1bb327f2162d4ce736a632ef817e48622ae9dbc1 # 5241 # GRF # sb/intel/bd82x6x: assign PCH SMBus controller ops in chipset devicetree +git revert --no-edit 2009b998345f9c37e773c3908e53749f24c6a138 # 5239 # GRF # nb/amd/pi/00730F01/chipset.cb: don't call dummy function host bridge +git revert --no-edit 1fe1904f385076f9390441e017efdbb7673f6da8 # 5235 # GRF # acpi/acpi_gic: Add GIC ITS subtable +git revert --no-edit 6920c6f232600cc828ac102bc0636043b4b956c9 # 5234 # GRF # acpi: Add IO Remapping Table structures +git revert --no-edit 372dfe0e20f7e56ba2acf872392da41f5ee28633 # 5232 # GRF # sb/intel/bd82x6x: assign PCH LPC bridge ops in chipset devicetree +git revert --no-edit d982274a4ecc8ed6b42724d03332d06d50393109 # 5217 # GRF # acpi: Add PPTT support +git revert --no-edit 3ea3fbe4f28b2cdf1c98f3e6b81aee25f41feabb # 5214 # GRF # soc/intel/meteorlake: Remove PM Energy Report WA +git revert --no-edit 98a46fb2dd2319b5971b57b345e0dddcf5c6880f # 5196 # GRF # vendorcode/amd/opensil: Implement cbmem_top_chipset +git revert --no-edit 0832e6790d5f1892edc543dff258c20dcea15c1b # 5185 # GRF # vendorcode/amd/opensil/genoa: Implement console callback +git revert --no-edit 791ce58e6e1f0ff2b1f6df824ca08475e87cf03a # 5175 # GRF # vendorcode/amd: Hook up opensil +git revert --no-edit 0b82a2e37078b90759ff877ded90dd4638aeb1b5 # 5167 # GRF # doc/releases/4.22: Replace unicode chars with ASCII +git revert --no-edit c0461f4a5174511a7c2fcd98055acbd1a3870165 # 5157 # GRF # Docs/releases: Finalize 4.22/4.22.01 release notes +git revert --no-edit 2731fa619bdeb80c263ea607d547c99a9cd7b1ac # 5156 # GRF # crossgcc: Upgrade GCC from 11.4.0 to 13.2.0 +git revert --no-edit 18051b3dd26dd80369f681c6532b928a99f88de8 # 5126 # GRF # acpi: Optimize enum acpi_tables layout +git revert --no-edit b558758554d6fc2cc3b672b947c11b32463fc3fb # 5114 # GRF # Documentation/releases: Add 24.02 release notes template +git revert --no-edit a56ff9087bc3af55ed47d7bb78bb42c8faa24aa5 # 5113 # GRF # sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree +git revert --no-edit 58a5374d5fbf2ddccbd5a2b156ac1a4b44b91522 # 5112 # GRF # sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree +git revert --no-edit 61f22cff5916dc528690721aa3aaa88f9c6576ad # 5111 # GRF # nb/intel/sandybridge: assign gma ops in chipset devicetree +git revert --no-edit 4c4d1948efd39afd2d15cc5efb86cc669cb155a3 # 5110 # GRF # nb/intel/sandybridge: assign host bridge ops in chipset devicetree +git revert --no-edit 947eebedcb34c59ecf46088d3ca57b4ad3c35a9b # 5105 # GRF # Docs/releases: Update 4.22 release notes +git revert --no-edit 8ccd314ce6b954a93528897fb029e66bf6078bd8 # 5099 # GRF # nb/amd/pi/00730F01: add CPU and domain ops in devicetree +git revert --no-edit 1952d13a414229f1867a8a9c00fc07df07d7042c # 5098 # GRF # nb/amd/pi/00730F01: restructure chip ops +git revert --no-edit 0010b89c67354dd4dda1417e6fc990cc3b82f0d4 # 5097 # GRF # nb/amd/pi/00730F01: introduce and use chipset devicetree +git revert --no-edit e2ce52f59f55791ac3e50457e221931a44929180 # 5049 # GRF # mb/lenovo/x220: Update devicetree +git revert --no-edit d205cf7e4ef6ebec49d45ec97f501f7de843ac94 # 5003 # GRF # cpu/x86/smm: Fix get_save_state calculation +git revert --no-edit 56178990be01da72c48019be47457f1b5f54e969 # 4899 # GRF # Documentation: Update 4.22 release notes with x86 CBFS cache support +git revert --no-edit d81d80c554a2549720ce2114a1a84720d0605192 # 4858 # GRF # soc/intel/cse: remove cbfs_unverified_area_map() API in cse_lite +git revert --no-edit 6dff1fd7d5e419b2f947f516551dcab3f4ebe30a # 4782 # GRF # cpu/intel/common: Define build time physical address reserved bits +git revert --no-edit 0b0113f2436b448cd172d2ae9cfcc07628020173 # 4762 # CBF # device/device.h: Rename pci_domain_scan_bus +git revert --no-edit 4dfa90613ce52a4fc7e1164a54e33c0b18f947d9 # 4751 # GRF # soc/intel/cannonlake: Support Comet Lake v1 and v2 in one build +git revert --no-edit b58fd2de04bbf330d26ad42cdaa43b17e7cde876 # 4633 # GRF # soc/intel/cse: Add entries to eventlog on PSR backup events +git revert --no-edit a2d10bb029e7da6d18f50cc694b9da54deb462b2 # 4632 # GRF # soc/intel/cse: Check PSR bit before issuing PSR backup command +git revert --no-edit 7b2edc3b6b5ecd37112d5e07f4601b68b2aea038 # 4631 # GRF # soc/intel/cse: Back up PSR data during CSE FW downgrade +git revert --no-edit 4f062ec34b6e344e88ceaf7460675a860f10a2b6 # 4627 # GRF # soc/intel/cse: Add function to get cse_bp_info early +git revert --no-edit 3748fca5955bc975ea426cf9bd9fd8e9278a9752 # 4597 # GRF # arch/x86/Kconfig: introduce RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT +git revert --no-edit ff4d6be9f99c34242140e965f1ed82240d67198c # 4596 # GRF # */include/cpu: use unsigned int for number of address bits +git revert --no-edit 8e4f6e90bf96fbd34df18774f52431ac98bc4b0c # 4569 # GRF # Documentation: Update 4.22 release notes with x86 .data section +git revert --no-edit 75f0b607fae6fb57bde7593b9c1ac926a59bf10f # 4568 # GRF # acpi: Fix typos +git revert --no-edit c3c71c3783c253c6dd9e5fa19ad98f2efcc0c2d4 # 4528 # GRF # soc/intel/cse: Make cse_bp_info response global +git revert --no-edit 3df6cc9de61ba16a94b40086999ddb6a9943dc26 # 4449 # GRF # acpi: Add functions to declare ARM GIC V3 hardware +git revert --no-edit fca612497db15caebdf97d741c85193ee2f0044b # 4448 # CBF # acpi/Makefile.inc: Move code inclusion +git revert --no-edit f3aa88a51cefc12da3304cd827bbfd6e7fcbfe76 # 4447 # GRF # arch/arm64: Hook up ACPI table generation +git revert --no-edit ba7a9eefcf4e571bc73d4be1141f676fc5547057 # 4378 # GRF # soc/intel/common: Fix invalid MADT entries creation +git revert --no-edit 1eff77bc59b77735872e675a8df4f059245e4be7 # 4376 # GRF # arch/x86: Reduce max phys address size for Intel TME capable SoCs +git revert --no-edit a6a5b25ce4235c4e645d3dc20f8222b1a81c54a3 # 4375 # GRF # cpu/intel: Move is_tme_supported() from soc/intel to cpu/intel +git revert --no-edit 2aeb6e405aea8740f87185158598f2af50390904 # 4291 # GRF # soc/intel/cannonlake/Kconfig: Deduplicate selections +git revert --no-edit 4d0b18480d7d0a85bef0d1adcf4837549118473e # 4281 # GRF # acpi/acpi.c: Accomodate 64bit MMCONF base in MCFG table +git revert --no-edit f3ae1a120973da374ecbd2488b56b6a8fbbc82b5 # 4266 # GRF # crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1 +git revert --no-edit e54c13e13cb1636f697187a844af9350974330a3 # 4265 # GRF # util/crossgcc: Update binutils from 2.40 to 2.41 +git revert --no-edit 02e4d32524e99906100db2c3aa0c51e748916231 # 4264 # GRF # util/crossgcc: Update GMP from 6.2.1 to 6.3.0 +git revert --no-edit facdfe46229931cab242bf975894e100ff95c80f # 4222 # GRF # doc/releases/4.22: Remove transitions from sections +git revert --no-edit 81da643c135b6e8cff6a7181f8f7914105977ba0 # 4209 # GRF # vc/amd: Only pull in Makefiles & dirs that are needed +git revert --no-edit 736d4d25df5ece86c3b2f611a5e4dda1eac627a7 # 4169 # GRF # acpi: Add function to add ARM PL011 to ACPI DBG2 +git revert --no-edit 757509113b6b944167cf1f13f9569236cd7e5b18 # 4130 # GRF # soc: Remove SOC_SPECIFIC_OPTIONS +git revert --no-edit 3ee08719ca2651dba1049be5f14eeb656a062575 # 4121 # GRF # docs/releases: Add 4.22 release notes template +git revert --no-edit e59868c6b6b69262adad27686f8fbf410edba6d0 # 4110 # GRF # util/crossgcc: Add --fetch option to download tarballs +git revert --no-edit 6f063d97a662464b5900697bdff313e3cba06421 # 4109 # GRF # soc/intel/broadwell/pch/Kconfig: Remove dummy PCH_SPECIFIC_OPTIONS +git revert --no-edit b470624c74257f3fdffc793455dbf0f984e0b89f # 4038 # GRF # mb/google: Use chromeec_smi_sleep() +git revert --no-edit d84ace50e35d60fe29e6718c33dd7e1e5ea937bd # 4037 # GRF # mb/google: Re-arrange mainboard_smi_sleep() +git revert --no-edit 7f4f99d5a5ef70a6bea232968efd80d5f6243301 # 4036 # GRF # mb/google/slippy: Use chromeec_smi_sleep() +git revert --no-edit 28a7d9bf795ac0f6dea4f6495c1afaaf3ec051ef # 4035 # GRF # mb/google/slippy: Re-arrange mainboard_smi_sleep() +git revert --no-edit af656f929299521d2509e5cc927b711f9d4c6ebb # 4034 # GRF # mb/google/auron: Use chromeec_smi_sleep() +git revert --no-edit 027f86e6af023b338a0f1d8a999a8f33eeacb010 # 4033 # GRF # ACPI: Add usb_charge_mode_from_gnvs() +git revert --no-edit f362bbd5c7ce5d96f4bed3adee9a8f3ccc2728e8 # 4010 # GRF # commonlib,console,nb,sb,security: Add SPDX licenses to Makefiles +git revert --no-edit 88decca14f84184e95482d6b16c0791a70eae9ce # 3887 # GRF # ACPI: Add helper fill_fadt_extended_pm_io() +git revert --no-edit f6ca89c2241103c326641f21396f60bb079aa6a4 # 3875 # GRF # cpu: Add SPDX license headers to Makefiles +git revert --no-edit ce61679c69605371104b228b36cbee6c1a4f1fc0 # 3855 # GRF # sb/intel/lynxpoint/Kconfig: Remove SOUTH_BRIDGE_OPTIONS +git revert --no-edit 254a7c0f8138936bd020b7c06938a83151f32397 # 3854 # GRF # sb/intel/ibexpeak/Kconfig: Remove SOUTH_BRIDGE_OPTIONS +git revert --no-edit eb988dfcbad35a1b9ccb5e17d5f06f28f0b995a8 # 3802 # GRF # acpi/acpi.c: Move setting FADT SCI INT to arch specific code +git revert --no-edit cd46e5f63a468a3f4aae9267b5db94c4e5cc1458 # 3801 # GRF # acpi/acpi.c: Add and use acpi_arch_fill_madt() +git revert --no-edit 6af7261b2b2547a1e7dfe99c7e359e83d9f2314a # 3793 # GRF # acpi.c: Guard FACS generation +git revert --no-edit eb2897b113a04229c7749d1c23990c984775ca13 # 3703 # GRF # mb/samsung/lumpy: override SMBus subsystem ID +git revert --no-edit 6974bcd28e740c61b80fd4c98311fc5ee8c429ea # 3702 # GRF # mb/google/parrot: override SMBus subsystem ID +git revert --no-edit a6076cfcfdbe46e81e598e4761eb5d4c4a4082ab # 3701 # GRF # mb/google/butterfly: override SMBus subsystem ID +git revert --no-edit 2e3cb639258fcc63816e3e0f0c5ec468931bf2a4 # 3667 # GRF # acpi.c: Add functions to create GTDT +git revert --no-edit 92a3b67eaea08b54252a5f18b53ce3e287380365 # 3659 # GRF # acpi/acpi.c: Split of ACPI table generation into separate files +git revert --no-edit b096d625d53cfc5bf2dbc38310427efa7521001d # 3617 # GRF # soc/intel/xeon_sp: Introduce soc_cpu_is_enabled +git revert --no-edit 8554954f9cf23d3858f2826ac11c1d026b8faece # 3608 # GRF # nb/intel/i945: Rework nb resource reading +git revert --no-edit 9ab8a78d7e37c92fb0e59b511dd3ae20f6478002 # 3604 # GRF # soc/amd/common/acpimmio: factor out IO port access to PM registers +git revert --no-edit 5bd68097cbb850552d6ec440118c409612e034f4 # 3597 # CBF # soc/amd/common/acpimmio/mmio_util: drop enable_acpimmio_decode_pm24 +git revert --no-edit ebafd4b905d913c37274ce97ff21c8f26ffabd78 # 3572 # GRF # util/crossgcc: Update GCC version from 11.3 to 11.4 +git revert --no-edit ca0436f7c134e565cb83878efe4d4d4a9ef160f4 # 3514 # GRF # nb/intel/x4x: Rework nb resource reading +git revert --no-edit 90753398b6e394efedae423004648d5f7c303fd4 # 3510 # GRF # util/crossgcc: Fix broken link by Intel to acpica tarball +git revert --no-edit a959f0ad7620e2e8b13b51c34f7397caf53e9a5f # 3491 # GRF # allocator_v4: Disable top-down allocation for EDK2 +git revert --no-edit 0bcdd40d789236aff2c205511dfc962a76a7c3be # 3477 # GRF # acpi/acpi.c: Fix regression with DSDT +git revert --no-edit adb80075151f5bb79b591cfafc54f4196fa7d353 # 3440 # GRF # acpi/acpi.c: Move ACPI header creation to a function +git revert --no-edit 01af0f8ac80384d23abc99860f2c5d605a1aa540 # 3439 # GRF # acpi/acpi.c: Reduce boilerplate +git revert --no-edit afa5383fdced8829689894a1833162b7361d9224 # 3402 # GRF # crossgcc: Upgrade IASL from 20230331 to 20230628 +git revert --no-edit 0754e00ace632c4a9e22670da3d676d6e9352aa2 # 3339 # GRF # allocator_v4: Fix top-level allocations w/o IORESOURCE_ABOVE_4G +git revert --no-edit 866eff06edb962633723295b36b89a80befb757d # 3332 # GRF # allocator_v4: Manually inline some thin functions +git revert --no-edit ee57065daddf0ae42851472e40da0b812c95a397 # 3331 # GRF # allocator_v4: Factor resource printing out +git revert --no-edit 9260ea60bfa487851e6afda59d83214a0c967208 # 3330 # GRF # allocator_v4: Use memranges only for toplevel +git revert --no-edit 5226301765ded70e0ef640e5252bbaca8cd14451 # 3329 # GRF # allocator_v4: Treat above 4G resources more natively +git revert --no-edit f9ee87ffbf6e7e5d7870bd3617c5a3368ac41c54 # 3252 # GRF # acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic() +git revert --no-edit 9362dd75d805fea8bc95ff58d5abd42cbbb4c36a # 3226 # GRF # acpi/acpi.c: Reduce scope of functions used locally +git revert --no-edit 8cab80c84f2be22e1f45a2b31c8019695b70abb2 # 3158 # GRF # soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge +git revert --no-edit 1c3849d5dc327866fc5f9e8805022b0f37d930a4 # 3124 # GRF # Documentation: Move 4.20 release notes to 4.20.1 +git revert --no-edit 9c599c8b30eca53292cc9af6b01718ac8de46807 # 2994 # GRF # crossgcc: Upgrade IASL from 20221020 to 20230331 +git revert --no-edit 67d95185865651aecb7ef3d8d343ec3cb9e60f77 # 2991 # CBF # arch/x86: Don't allow hw floating point operations +git revert --no-edit 531023285ea4108d5b847625739d76992ce39200 # 2927 # GRF # soc/intel/quark: Drop support +git revert --no-edit 6a07db21b12b08c7b975921f2ee1196dd0ec92b3 # 2904 # CBF # console: Add format-checking __printf() to die() +git revert --no-edit a4298bc3f82f476ce82e3e948f6573f5e38dfb25 # 2823 # GRF # mb/prodrive/atlas: Shorten FSP-M UPD statements +git revert --no-edit 85556ac1dc9472a7624cdc3c82aa890407ecceda # 2794 # GRF # soc/intel: Clean up some includes +git revert --no-edit 83faa5d804d183a26b0fa66b5d55bbe5f3b72c89 # 2785 # GRF # mb/google,intel: Use common ChromeEC code for lid shutdown +git revert --no-edit b78e4620375cc5668db668d900340fd89271c330 # 2743 # GRF # Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER} +git revert --no-edit 5fc0afbc170960d05012eec9b3b8717f65a07478 # 2684 # GRF # asus/p2b, emu/qemu-i440fx: Use acpigen_write_processor_device() +git revert --no-edit 02a19010916f6de42cd5ce0ba74da8ba5ad5c8ec # 2680 # GRF # sb,soc/amd,intel: Drop include <cpu/x86/smm.h> +git revert --no-edit 240baa31e8a804029069e21f523556d8628f6001 # 2679 # GRF # ACPI: Make FADT entries for RTC/CMOS architectural +git revert --no-edit 121d3d57adc35ed34204f983a72590f978939b1c # 2652 # GRF # ACPI: Make FADT entries for SMI architectural +git revert --no-edit 7186e28001ff01e9f48f838eab8ee462c3e8155c # 2651 # GRF # soc/amd: Drop acpi_fill_madt_irqoverride() +git revert --no-edit 3454367d6401ba7d468e8915706fd022b3b5d59f # 2628 # GRF # AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit 8eac12fa7d49de59f63739bcb466e188dbc1ed66 # 2627 # GRF # soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit 304f8387fe698b66c7c853098001fc83638dd874 # 2626 # GRF # soc/amd: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit 1f9e24052a9d51c015d2841ee66e7408d7bdab84 # 2625 # GRF # asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit ac61a65fef73fe0700695afd1fc849ed629d59aa # 2624 # GRF # aopen/dxplplusu: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit 6437409b760a927a34bf5e804703873af898e14f # 2623 # GRF # soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPIC +git revert --no-edit 81dc352032cacb309ed9335f394969d847820511 # 2622 # GRF # intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit 7f8e2a6a4a9cb1544ef8fa19850abeb3d4213931 # 2621 # GRF # sb/intel: Use ACPI_COMMON_MADT_IOAPIC +git revert --no-edit 10bdee13272a77aed46912363db691cf4c088a93 # 2620 # GRF # ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT +git revert --no-edit e742b68f1ac9324ce1f700323f1226e86d068a8c # 2619 # GRF # arch/x86/ioapic: Promote ioapic_get_sci_pin() +git revert --no-edit ae1b2d49cf0ad09ff8f1e3904a9e7b23d6fb423b # 2618 # GRF # soc/intel: Introduce ioapic_get_sci_pin() +git revert --no-edit 9368cf90255daeb53765d442a639f86ee5be1f29 # 2615 # GRF # acpi/acpi.c: Reduce scope of some functions +git revert --no-edit 27af3e6b111f462a71762bd56363d06d73505284 # 2599 # GRF # include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb +git revert --no-edit 7c302cf20859592a32e19fb6eb434dfb06b1d3c3 # 2583 # GRF # cpu/amd/pi/00730F01: rename fixme.c to cpu_io_init.c +git revert --no-edit fb532c711e2ef317108d6ffc35ae751bf7d58530 # 2545 # GRF # include/cpu/amd/mtrr: return uint32_t from get_top_of_mem_below_4gb +git revert --no-edit 5e9afe7272d110265ffa6f5465fa942c2bf4961f # 2544 # CBF # include/cpu/amd/mtrr: rename functions to get top of memory regions +git revert --no-edit 71fd3becf0f6aafa1b17495233129b06893402b1 # 2492 # GRF # soc/intel/baytrail: Make acpi_madt_irq_overrides() static +git revert --no-edit 69a13964ea6c5fda6ddf475a9ea905aa7376620c # 2491 # GRF # sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC +git revert --no-edit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de # 2480 # GRF # soc/intel/xeon_sp: Don't sort struct device cpus for numa +git revert --no-edit 8547429d396a68fc82cc6aff5b7fa61ae8235834 # 2474 # GRF # acpi/acpi.c: Follow spec more closely for MADT +git revert --no-edit f4dff389ee90640cd2f9cd4b34f59ce14a738379 # 2456 # GRF # cpu/x86/mp_init.c: Set topology on BSP +git revert --no-edit 2e9f0d3b6aa754dc71cd36086d1eb2a839bdb7bd # 2419 # GRF # ACPI: Add helper for MADT LAPICs +git revert --no-edit 9ac1fb729fa316564992403580254b1c4afbf9c2 # 2418 # CBF # ACPI: Add helper for MADT LAPIC NMIs +git revert --no-edit 899c713e3eb073491d8b954165919daa87609493 # 2417 # CBF # binaryPI: Use common code for LAPIC NMIs +git revert --no-edit e84b095d3a238ae5fd734c4c186132a4e07eea07 # 2409 # GRF # util/sconfig: Remove unused ioapic and irq keywords +git revert --no-edit 8b8400a889abadbbd2156d4a35a27203068766f1 # 2408 # GRF # drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer +git revert --no-edit 177e13513644b4d3de2529468e827ebfcadbda02 # 2360 # CBF # cpu/x86/topology: Add code to fill in topology on struct path +git revert --no-edit ddf48eb7c75687398d6a390bc21a50d74aef5df6 # 2359 # GRF # cpu/mp_init.c: Only enable CPUs once they execute code +git revert --no-edit a804f9195eb8fd93a2a6650cc24a26e422696214 # 2358 # GRF # cpu/smm_module_loader.c: Fix up CPU index locally +git revert --no-edit 21ca7753bf619f1de8dca79fd1113a9c22335f11 # 2356 # GRF # cpu/x86/mp_init.c: Keep track of initial lapic ID inside device_path +git revert --no-edit 0686c69802867293644a924bc29812697eace76f # 2300 # GRF # util/crossgcc: Update binutils from 2.37 to 2.40 +git revert --no-edit 586b1c8da06fe34f91c747440730b31428248b34 # 2181 # GRF # mb/prodrive/atlas: Add workaround for CLKREQ pins +git revert --no-edit 4f13239318a92451dddcc821d9fb977c1d0b6994 # 2138 # GRF # mb/prodrive/atlas: Configure PCIe CLKREQ +git revert --no-edit 13dcdff7c7e1877887c3eb696b8de35872937d41 # 2127 # GRF # mb/asrock/b75pro3-m: Disable unused ME KT PCI device +git revert --no-edit ac8c378777d861000d82eea1c7439f16dcd45797 # 1940 # GRF # cpu/x86/smm: Add PCI resource store functionality +git revert --no-edit 829e8e65b93963d15367092cd3d364c230465720 # 1809 # GRF # ##### soc/intel: Use common codeflow for MP init +git revert --no-edit 36847977cb95e319ec67ab2edf85e6ea96783628 # 1760 # GRF # ##### util/crossgcc: Update GCC from 11.2 to 11.3 +git revert --no-edit c013fa6234f08e22dd3706849936847cf82b5024 # 1748 # GRF # mb/scaleway/tagada: Drop support +git revert --no-edit 107e7aa0f58f79ee5719f82c7147e53d7d9fa218 # 1723 # GRF # cpu/x86/smm: Enable setting SMM console log level from mainboard +git revert --no-edit 893c3ae892961facc9be8bd300160222e694ab34 # 1543 # GRF # tree: Drop repeated words +git revert --no-edit 584d5e1cbabc1a8ce679597263d22a2a9b87c9f7 # 1532 # GRF # soc/intel/apl: Hook up cpu ops in devicetree +git revert --no-edit 01c8c5936451d1f31dcb0a1c79f1f8e01dead83b # 1527 # GRF # Makefile.inc: Use 'Wmissing-include-dirs' command option +git revert --no-edit b5df65a9aaee50421913ace6d7a4b35e0ddff676 # 1501 # GRF # mb/*: Replace SNB PCI devices with references from chipset.cb +git revert --no-edit 64e2ecb36fd1d7b289cd9671dcfae2e335528d81 # 1493 # GRF # soc/intel/apl: Move cpu cluster to chipset.cb +git revert --no-edit 15d5183e4af79624304a8379b71767cd8ee09250 # 1433 # CBF # util/sconfig: Remove lapic devices from devicetree parsers +git revert --no-edit 2c1511a461cd6dde750090e0337bf3f893710dc1 # 1430 # GRF # crossgcc: Upgrade mpfr from 4.1.1 to 4.2.0 +git revert --no-edit d15a9f9b342e5226be67b6d43e68389d871f7f84 # 1429 # GRF # crossgcc: Upgrade mpc from 1.2.1 to 1.3.1 +git revert --no-edit 6ac0a46bbf9e20c8412ee0d04658b3a2b10d0734 # 1422 # GRF # util/crossgcc/buildgcc: Remove extra "/" at the end of IASL_BASE_URL +git revert --no-edit 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 # 1421 # GRF # mb/*: Remove lapic from devicetree +git revert --no-edit 48fa6dd8f9a8f78f94d508b0a105e2ddaacf99ba # 1326 # CBF # arch/x86/Kconfig: Remove unused NUM_IPI_STARTS +git revert --no-edit c9cd886a4b2d52734c6d1f5d028b98f0f3b1bcce # 1178 # CBF # treewide: Remove unused <cpu/x86/smm.h> +git revert --no-edit 8b93a173fbed29ea356653caa0626e48e81a5f8d # 1177 # CBF # treewide: Remove unused <cpu/amd/mtrr.h> +git revert --no-edit 16a444c5011e70298ebd9546a39f9d8b61d95030 # 1155 # GRF # util/crossgcc/Makefile.inc: Terminate quoted string +git revert --no-edit fc84ae7aa3cf7e8000ef69f854281f4648eeb2b8 # 1124 # CBF # treewide: Remove unused <cpu/amd/msr.h> +git revert --no-edit 4d75dbd1c1d6362c002a26a5c4e6de74b2816cdf # 950 # GRF # cpu/x86: Set up a separate stack for APs +git revert --no-edit 3b32af950d704b1d14ddca917dd480f5ebbf09a5 # 821 # GRF # util/crossgcc: Add option to get packages from coreboot's mirror +git revert --no-edit db65dd60fb11e3d38dbdd9a2e2f64d6ea7ef7576 # 748 # GRF # cpu/x86/mp_init.c: Improve AP entry point +git revert --no-edit 6e23da2983f83c803cf4abfee542d7f90e8e9eb5 # 622 # CBF # cpu/cpu.h: Change the function signature +git revert --no-edit f1e78a1349d40f2e8a74b15471fc5560976a566f # 560 # GRF # arch/x86/ioapic.c: Move macros to compilation unit +git revert --no-edit 2c3ebd8b9d56c01d8e4adadf6f4e4d5b56cdb4e1 # 555 # GRF # mb,sb,soc/intel: Drop useless IO trap handlers +git revert --no-edit 2393ad0bfb1cd23a0524e7b02a0fd75aff3bf274 # 520 # CBF # Makefile.inc: Use 'Wold-style-definition' +git revert --no-edit f9679c42876bab145f1b7a2a2e6e1eb5331fa418 # 500 # GRF # nb/intel/gm45: Remove apic 0 from devicetree +git revert --no-edit 31ba9356b877d670e683953f8b8962a7e6206cc3 # 499 # GRF # nb/intel/i945: Remove apic 0 from devicetree +git revert --no-edit 803029685f96bccac13359fc616d1577508ba764 # 498 # GRF # nb/intel/x4x: Remove apic 0 from devicetree +git revert --no-edit 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 # 497 # CBF # cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm +git revert --no-edit cc22607dbfbab0c9ce42c071b5b3c4a304845313 # 420 # GRF # Revert "src/arch/x86: Use core apic id to get cpu_index()" +git revert --no-edit 60a422736bde766489db8ff0dc2d56ab333c37cc # 407 # GRF # util/crossgcc: Use GitHub for downloading IASL +git revert --no-edit a45ed44724a30303030e80898202b77c34498942 # 373 # CBF # crossgcc: Upgrade IASL from 20220331 to 20221020 +git revert --no-edit fa775b7651e4488f0535c17a5e04974e7d1a40b2 # 171 # CBF # cpu/cpu.h: Remove unused functions prototypes +git revert --no-edit 987f46c276bd1b6b5d15be8ca9aee5f028e37fa7 # 167 # GRF # arch/x86/mpspec.c: Drop weak write_smp_table() +git revert --no-edit ca5a793ec31c76b168ae2f9d2260b49c79330eb2 # 166 # CBF # drivers/generic/ioapic: Drop poor implementation +git revert --no-edit d4dfc21f70616bc97191969aa2b6d0196a525fce # 134 # GRF # cpu/x86: Set thread local storage in C code +git revert --no-edit 1d3c2e65724ed92eeef723c1acdc86ba91cbd682 # 111 # CBF # arch/x86/ioapic: Reduce API exposure +git revert --no-edit c8a20b9d3b8939e4b7d259c5857631c9690657de # 76 # CBF # cpu/*: Drop PARALLEL_MP leftovers +git revert --no-edit 36695f278f0ca3cb3a3b0a8ca50b317505882df2 # 18 # CBF # device/resource_allocator_v3: Drop code +git revert --no-edit f4c11dcb53bbd324741ecd7109584eaa55579f7f # 17 # CBF # cpu/x86: Drop !CPU_INFO_V2 code +git revert --no-edit 66b2888b77da6721955a918c8cd5399abe786a6a # 16 # CBF # cpu/x86: Drop LEGACY_SMP_INIT +git revert --no-edit e2d291b5ae4aa49d5b1613e06b86bf2fc8efe4c5 # 15 # CBF # mb/qemu/x86: Remove option for LEGACY_SMP_INIT +git revert --no-edit 03a6ccd20d9bb54e3a009269b8e454ee8a2e3051 # 14 # CBF # sb/amd: Remove dropped platforms +git revert --no-edit 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 # 13 # CBF # nb/amd/agesa: Remove leftover code +git revert --no-edit 81a4fefce223ba358310aec2d988484202c176e2 # 12 # CBF # cpu/amd/agesa: Remove leftover code +git revert --no-edit 0f12381083fdfc7bb3e6f3b2ac5cd6247506c543 # 11 # CBF # vendorcode/amd/agesa: Drop unused common code +git revert --no-edit 7036ded25d3a051902862e2a7bdfe15916f0951d # 10 # CBF # vendorcode/amd/agesa/family16: Drop unused platform +git revert --no-edit 49af4f7f9197e559b2c7142129441679bb1d24a2 # 9 # CBF # {cpu/nb}/amd/family16: Remove platform +git revert --no-edit 5d152122284880029c123fe2b7dfa20cd8b74632 # 8 # CBF # vendorcode/amd/agesa/fam15tn: Drop unused platform +git revert --no-edit 9a458e4e58edbfc154dce007961514b5c31cf7aa # 7 # CBF # {cpu/nb}/amd/family15tn: Remove platform +git revert --no-edit 713e3c087b6128fec2fd17d4373357e10fc928ab # 6 # CBF # vendorcode/amd/agesa/fam14: Remove dropped platform +git revert --no-edit dbdf170dcdf9edbc860766606e53c6d647d89d38 # 5 # CBF # {cpu/nb}/amd/family14: Remove platform +git revert --no-edit 6baee3d28729d4b924e8f793c4c7311cebf1f80a # 3 # CBF # mb/*/*: Remove AMD agesa family16 boards +git revert --no-edit f9decbb0c720662d8e71fe221aef55b7ecf76196 # 2 # CBF # mb/*/*: Remove AMD family14 boards +git revert --no-edit e56f0c7cab77b89a750b4a3f7f380b1a10cd0d1d # 1 # CBF # mb/*/*: Remove AMD FAMILY15TN boards + +# +# git reset --hard 5e8e911b7caee021faff96c4e82a77a42544ea62 ### 00000 # - zero commit number = zero point of history before removal +# + +git revert --no-edit ce134ababd6a444082962ccdfcd34415a647f41e # -4568 # GRF # crossgcc/buildgcc: Remove unused GCC_AUTOCONF_VERSION +git revert --no-edit b0d87f753c9c517ba906115362d32aa4422fd188 # -5952 # CBF # util/crossgcc: Update gcc to 11.2 + +# -- To view, visit https://review.coreboot.org/c/coreboot/+/79838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia97e80ffaad9459e54ff5cb01f20d9129241433c Gerrit-Change-Number: 79838 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42
by Mike Banon (Code Review) 07 Jan '24

07 Jan '24

Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79666?usp=email ) Change subject: soc/intel/meteorlake: Fix SOC_PHYSICAL_ADDRESS_WIDTH to 42 ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: With this commit in tree, I am getting this warning each time I run "make menuconfig" for an unrelated board: src/soc/intel/meteorlake/Kconfig:468:warning: config symbol defined without type Indeed, it's just "42" without any type. To fix this warning, please add "int" line: config SOC_PHYSICAL_ADDRESS_WIDTH int default 42 -- To view, visit https://review.coreboot.org/c/coreboot/+/79666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic63c93cb15d2998e13d49a872f32d425237f528a Gerrit-Change-Number: 79666 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sun, 07 Jan 2024 14:46:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 07 Jan '24

07 Jan '24

Attention is currently required from: Arthur Heymans, Nicholas Chin. Iru Cai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79746?usp=email ) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... Patch Set 3: (13 comments) Patchset: PS2: > I noticed that your old MEC5055 patch in CB:44975 which your old E7240 port used sent a 0xAB command […] I didn't know what the effect of this command is, just found it in the vendor firmware. File Documentation/mainboard/dell/e7240.md: https://review.coreboot.org/c/coreboot/+/79746/comment/a39fe40b_163b08c2 : PS2, Line 29: a programmer > Maybe make this more clear by using "an external programmer" Done https://review.coreboot.org/c/coreboot/+/79746/comment/0254b434_b58567c1 : PS2, Line 41: Schematic of this laptop can be found on [Lab One]. The board name is Compal LA-9431P. > It's not a formally written policy but it's probably not good idea for coreboot to link to documents […] removed https://review.coreboot.org/c/coreboot/+/79746/comment/e4b0df7f_33a82d11 : PS2, Line 81: : [Lab One]: https://www.laboneinside.com/dell-latitude-e7240-schematic-diagram/ : > See prior comment about the schematic link Done File src/mainboard/dell/e7240/Kconfig: https://review.coreboot.org/c/coreboot/+/79746/comment/a99c069c_cea00ea9 : PS2, Line 5: BOARD_ROMSIZE_KB_8192 > Is this correct? The E7240 appears to have 2 flash chips, an 8MiB and a 4MiB I can see one chip in my board, another place that can solder a flash chip is empty. The image is uploaded. https://review.coreboot.org/c/coreboot/+/79746/comment/bb436704_fd6441d0 : PS2, Line 17: string > Not necessary, as the type is already defined in `mb/Kconfig` Done https://review.coreboot.org/c/coreboot/+/79746/comment/9e0c3720_a0d699b5 : PS2, Line 21: string > Same here, can be removed Done https://review.coreboot.org/c/coreboot/+/79746/comment/93e93223_c4556ff6 : PS2, Line 24: config VGA_BIOS_FILE : string : default "pci8086,0a16.rom" > Remove, see commit 05ae8f2ff3 (mainboard: Drop invalid `VGA_BIOS_FILE` defaults). Done https://review.coreboot.org/c/coreboot/+/79746/comment/08238363_cc4e1ab0 : PS2, Line 29: string > Can be removed Done https://review.coreboot.org/c/coreboot/+/79746/comment/e059493f_a1710b2e : PS2, Line 33: int > Can be removed Done File src/mainboard/dell/e7240/Makefile.inc: PS2: > Missing SPDX header. […] Done File src/mainboard/dell/e7240/bootblock.c: https://review.coreboot.org/c/coreboot/+/79746/comment/1130749a_aa4d837d : PS2, Line 13: pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x007c0901); : mec5035_early_init(); : pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0); > Any reason to explicitly set and unset LPC_GEN4_DEC here? The devicetree entries for these are set u […] Done File src/mainboard/dell/e7240/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79746/comment/5e463dbf_bc32e8ed : PS2, Line 66: device pci 1f.0 on end # LPC bridge > Did you try adding the EC here like the dell/e6400? That seems to call a function that initialized t […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sun, 07 Jan 2024 14:35:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mainboard: add Dell Latitude E7240
by Iru Cai (Code Review) 07 Jan '24

07 Jan '24

Attention is currently required from: Iru Cai. Hello Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79746?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard: add Dell Latitude E7240 ...................................................................... mainboard: add Dell Latitude E7240 Based on autoport output. It boots to Arch Linux (Linux 6.6.3) from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/dell/e7240.md A Documentation/mainboard/dell/e7240.webp M Documentation/mainboard/index.md A src/mainboard/dell/e7240/Kconfig A src/mainboard/dell/e7240/Kconfig.name A src/mainboard/dell/e7240/Makefile.inc A src/mainboard/dell/e7240/acpi/ec.asl A src/mainboard/dell/e7240/acpi/platform.asl A src/mainboard/dell/e7240/acpi/superio.asl A src/mainboard/dell/e7240/board_info.txt A src/mainboard/dell/e7240/bootblock.c A src/mainboard/dell/e7240/devicetree.cb A src/mainboard/dell/e7240/dsdt.asl A src/mainboard/dell/e7240/gma-mainboard.ads A src/mainboard/dell/e7240/gpio.c A src/mainboard/dell/e7240/hda_verb.c A src/mainboard/dell/e7240/romstage.c 17 files changed, 466 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79746/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 79746 Gerrit-PatchSet: 3 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: board_status/getrevision.sh: Ignore non-annotated tags
by Michael Büchler (Code Review) 07 Jan '24

07 Jan '24

Michael Büchler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79837?usp=email ) Change subject: board_status/getrevision.sh: Ignore non-annotated tags ...................................................................... board_status/getrevision.sh: Ignore non-annotated tags Local tags (e.g. to keep track of builds) should not be used to describe a board status report. This has happened in some cases, e.g. [1]. According to the Git 2.41.0 manual for git-describe, the '--tagged' parameter is a way to also use any "lightweight (non-annotated) tag" in addition to annotated tags, which are always used even without this parameter. All coreboot release tags seem to be annotated, so this option should be safe to drop. [1] https://review.coreboot.org/plugins/gitiles/board-status/+/b8c47429bad5afc5… Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: I54b302415e569a3385559cc85323ce34462042ad --- M util/board_status/getrevision.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/79837/1 diff --git a/util/board_status/getrevision.sh b/util/board_status/getrevision.sh index ced20fc..a982f8d 100755 --- a/util/board_status/getrevision.sh +++ b/util/board_status/getrevision.sh @@ -112,7 +112,7 @@ local r if git_is_file_tracked "$1" ; then - r=$(git describe --tags --dirty) + r=$(git describe --dirty) else return ${EXIT_FAILURE} fi -- To view, visit https://review.coreboot.org/c/coreboot/+/79837?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b302415e569a3385559cc85323ce34462042ad Gerrit-Change-Number: 79837 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85
by Subrata Banik (Code Review) 07 Jan '24

07 Jan '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79829?usp=email ) Change subject: vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85 ...................................................................... vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85 Update header files for FSP for Meteor Lake platform to version 3471_85, previous version being 3424_88. FSPM: 1. Add 'DisplayGpioPinMux' UPDs 2. Address offset changes BUG=b:318772151 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 1 file changed, 9 insertions(+), 2 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index 1ac6ef8..d33068e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -926,9 +926,16 @@ **/ UINT8 DdiPort4Ddc; -/** Offset 0x02BE - Reserved +/** Offset 0x02BE - GPIO PIN MUX to choose between GPP_SA and GPP_SD Group. + Default will be 0 for each Display PIN Mux which is GPP_SA Group. (0 = SA GROUP, + 1 = SD GROUP). BIT0 - EDP VDDEN, BIT1 - EDP BKLTEN, BIT2 - EDP BKLTCTRL, BIT3 + - DDI-A, BIT4 - DDI-1/HPD1, BIT5 - DDI-2/HPD2, BIT6 - DDI-3/HPD3, BIT7 - DDI-4/HPD4 **/ - UINT8 Reserved16[18]; + UINT8 DisplayGpioPinMux; + +/** Offset 0x02BF - Reserved +**/ + UINT8 Reserved16[17]; /** Offset 0x02D0 - Per-core HT Disable Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, -- To view, visit https://review.coreboot.org/c/coreboot/+/79829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Gerrit-Change-Number: 79829 Gerrit-PatchSet: 3 Gerrit-Owner: srinivas.kulkarni(a)intel.com Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: nb/intel/gm45/raminit: Use read32p()
by Felix Singer (Code Review) 07 Jan '24

07 Jan '24

Attention is currently required from: Arthur Heymans, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77971?usp=email ) Change subject: nb/intel/gm45/raminit: Use read32p() ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/77971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092 Gerrit-Change-Number: 77971 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Jan 2024 05:10:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.inc: Enable Wold-style-declaration command option
by Felix Singer (Code Review) 07 Jan '24

07 Jan '24

Attention is currently required from: Arthur Heymans, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71892?usp=email ) Change subject: Makefile.inc: Enable Wold-style-declaration command option ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Sent patch here https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere… -- To view, visit https://review.coreboot.org/c/coreboot/+/71892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3fa59edb07e4105ef3cfb6a20cb29680699586 Gerrit-Change-Number: 71892 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 07 Jan 2024 05:05:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: sb/intel/i82801{i;j}x/chip.h: Use boolean where appropriate
by Felix Singer (Code Review) 07 Jan '24

07 Jan '24

Attention is currently required from: Alexander Couzens, Elyes Haouas, Felix Singer, Nicholas Chin, Stefan Ott. Felix Singer has uploaded a new patch set (#5) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77738?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: sb/intel/i82801{i;j}x/chip.h: Use boolean where appropriate ...................................................................... sb/intel/i82801{i;j}x/chip.h: Use boolean where appropriate Use boolean instead of bit fields. Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/dell/e6400/devicetree.cb M src/mainboard/intel/dg43gt/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t400/variants/r500/overridetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x200/variants/x200/overridetree.cb M src/mainboard/lenovo/x200/variants/x301/overridetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/lpc.c 13 files changed, 38 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77738/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/77738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Gerrit-Change-Number: 77738 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: nb/intel/gm45/raminit: Use read32p()
by Felix Singer (Code Review) 07 Jan '24

07 Jan '24

Attention is currently required from: Elyes Haouas. Felix Singer has uploaded a new patch set (#4) to the change originally created by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/77971?usp=email ) Change subject: nb/intel/gm45/raminit: Use read32p() ...................................................................... nb/intel/gm45/raminit: Use read32p() Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom remains identical. Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/northbridge/intel/gm45/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/77971/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/77971?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092 Gerrit-Change-Number: 77971 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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