coreboot-gerrit January 2024

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[M] Change in coreboot[main]: device: Add support for multiple PCI segment groups
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Cliff Huang, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Wawrzynczak. Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/79927?usp=email to review the following change. Change subject: device: Add support for multiple PCI segment groups ...................................................................... device: Add support for multiple PCI segment groups Add initial support for multiple PCI segment groups. Instead of modifying secondary in the bus struct introduce a new variable and keep existing common code. Since all platforms currently only use 1 segment this is not a functional change. On platforms that support more than 1 segment the segment has to be set when creating the PCI domain. Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 --- M src/acpi/acpi.c M src/device/Kconfig M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/pci_device.c M src/include/device/device.h M src/include/device/pci_def.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/genoa_poc/domain.c 14 files changed, 63 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/79927/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 5e76916..0bd82cb 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -150,9 +150,14 @@ static unsigned long acpi_fill_mcfg(unsigned long current) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); + for (int i = 0; i < PCI_SEGMENT_GROUP_COUNT; i++) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_ECAM_MMCONF_BASE_ADDRESS + i * PCI_PER_SEGMENT_GROUP_ECAM_SIZE, + i, + 0, + PCI_BUSES_PER_SEGMENT_GROUP - 1); + } + return current; } @@ -695,6 +700,7 @@ if (device->path.type == DEVICE_PATH_PCI) { spmi->pci_device_flag = ACPI_IPMI_PCI_DEVICE_FLAG; + spmi->pci_segment_group = device->bus->segment_group; spmi->pci_bus = device->bus->secondary; spmi->pci_device = device->path.pci.devfn >> 3; spmi->pci_function = device->path.pci.devfn & 0x7; diff --git a/src/device/Kconfig b/src/device/Kconfig index 83afa8c..117df56 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -596,6 +596,8 @@ default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64 default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128 default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256 + default 0x20000000 if ECAM_MMCONF_BUS_NUMBER = 512 + default 0x80000000 if ECAM_MMCONF_BUS_NUMBER = 1024 default 0x0 config PCI_ALLOW_BUS_MASTER diff --git a/src/device/device.c b/src/device/device.c index a635e73..811b709 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -152,8 +152,8 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s bus %d link: %d\n", dev_path(bus->dev), - __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s segment group %d bus %d link: %d\n", dev_path(bus->dev), + __func__, bus->segment_group, bus->secondary, bus->link_num); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { @@ -176,8 +176,8 @@ read_resources(link); } post_log_clear(); - printk(BIOS_SPEW, "%s %s bus %d link: %d done\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s segment group %d bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->segment_group, bus->secondary, bus->link_num); } struct device *vga_pri = NULL; @@ -266,8 +266,8 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, segment group %d bus %d link: %d\n", + dev_path(bus->dev), __func__, bus->segment_group, bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -282,8 +282,8 @@ curdev->ops->set_resources(curdev); } post_log_clear(); - printk(BIOS_SPEW, "%s %s, bus %d link: %d done\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, segment group %d bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->segment_group, bus->secondary, bus->link_num); } /** diff --git a/src/device/device_const.c b/src/device/device_const.c index a63a629..266404a 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -35,6 +35,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && (dev->bus->secondary == bus) && + (dev->bus->segment_group == 0) && (dev->path.pci.devfn == devfn)) { result = dev; break; @@ -224,8 +225,16 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn) { + return pcidev_path_on_segbus(0, bus, devfn); +} + +DEVTREE_CONST struct device *pcidev_path_on_segbus(unsigned int segment_group, + unsigned int bus, + pci_devfn_t devfn) +{ DEVTREE_CONST struct bus *parent = pci_root_bus(); DEVTREE_CONST struct device *dev = parent->children; + assert(segment_group < PCI_SEGMENT_GROUP_COUNT); /* FIXME: Write the loop with topology links. */ while (dev) { @@ -233,7 +242,7 @@ dev = dev->next; continue; } - if (dev->bus->secondary == bus) + if (dev->bus->secondary == bus && dev->bus->segment_group == segment_group) return pcidev_path_behind(dev->bus, devfn); dev = dev->next; } diff --git a/src/device/device_util.c b/src/device/device_util.c index b37d1d9..1837e29 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -97,7 +97,7 @@ case DEVICE_PATH_ROOT: break; case DEVICE_PATH_PCI: - ret |= dev->bus->secondary << 8 | dev->path.pci.devfn; + ret |= dev->bus->segment_group << 16 | dev->bus->secondary << 8 | dev->path.pci.devfn; break; case DEVICE_PATH_PNP: ret |= dev->path.pnp.port << 8 | dev->path.pnp.device; @@ -168,7 +168,8 @@ break; case DEVICE_PATH_PCI: snprintf(buffer, sizeof(buffer), - "PCI: %02x:%02x.%01x", + "PCI: %02x:%02x:%02x.%01x", + dev->bus->segment_group, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); @@ -525,7 +526,8 @@ if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) { snprintf(buf, sizeof(buf), - "bus %02x ", dev->link_list->secondary); + "seg %02x bus %02x ", dev->link_list->segment_group, + dev->link_list->secondary); } printk(BIOS_DEBUG, "%s %02lx <- [0x%016llx - 0x%016llx] size 0x%08llx " "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, diff --git a/src/device/pci_device.c b/src/device/pci_device.c index b356c26..eb1bfbf 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1314,7 +1314,8 @@ */ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) { - return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + return dev->bus->secondary == PCI_DEV2BUS(sdev) && + dev->bus->segment_group == PCI_DEV2SEG(sdev) && dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); } @@ -1428,7 +1429,8 @@ struct device *dev, **prev; int once = 0; - printk(BIOS_DEBUG, "PCI: %s for bus %02x\n", __func__, bus->secondary); + printk(BIOS_DEBUG, "PCI: %s for segment group %02x bus %02x\n", __func__, + bus->segment_group, bus->secondary); /* Maximum sane devfn is 0xFF. */ if (max_devfn > 0xff) { @@ -1550,6 +1552,7 @@ link->max_subordinate = parent->max_subordinate ? parent->max_subordinate : (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); + link->segment_group = parent->segment_group; } if (link->secondary > link->max_subordinate) diff --git a/src/include/device/device.h b/src/include/device/device.h index 41ec528..c8e45ef 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -86,6 +86,7 @@ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* subordinate bus number */ uint16_t max_subordinate; /* max subordinate bus number */ + uint8_t segment_group; /* PCI segment group */ unsigned int reset_needed : 1; unsigned int no_vga16 : 1; /* No support for 16-bit VGA decoding */ @@ -425,6 +426,9 @@ pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn); +DEVTREE_CONST struct device *pcidev_path_on_segbus(unsigned int segment, + unsigned int bus, + pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); /* Find PCI device with given D#:F# sitting behind the given PCI-to-PCI bridge device. */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 8b90163..6efa1cd 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -591,9 +591,16 @@ #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) #define PCI_FUNC(devfn) ((devfn) & 0x07) +#define PCI_BUS_NUMBER_MASK 0xff +#define PCI_SEGMENT_GROUP_COUNT ((CONFIG_ECAM_MMCONF_BUS_NUMBER >> 8) + 1) +#define PCI_BUSES_PER_SEGMENT_GROUP (((CONFIG_ECAM_MMCONF_BUS_NUMBER - 1) & PCI_BUS_NUMBER_MASK) + 1) +#define PCI_PER_SEGMENT_GROUP_ECAM_SIZE (256 * MiB) + /* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ #define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff) #define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff) +#define PCI_DEV2BUS(sdev) (((sdev)>>20) & PCI_BUS_NUMBER_MASK) +#define PCI_DEV2SEG(sdev) (((sdev)>>28) & 0xf) /* Fields from within the device's class value. */ #define PCI_CLASS_GET_DEVICE(c) (c >> 8) diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index b5d4e23..de5f913 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -12,7 +12,8 @@ static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) { - return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20); + return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20) | + (dev->bus->segment_group << 28); } static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 12fbdfa..51f1593 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -1114,7 +1114,7 @@ return smbios_write_type41(current, handle, name, // name instance_id, // inst - 0, // segment group + dev->bus->segment_group, // segment group dev->bus->secondary, //bus PCI_SLOT(dev->path.pci.devfn), // device PCI_FUNC(dev->path.pci.devfn), // func @@ -1167,7 +1167,7 @@ 0, 1, 0, - 0, + dev->bus->segment_group, dev->bus->secondary, dev->path.pci.devfn); } diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index dae2401..a4409fb 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -296,7 +296,7 @@ ivhd_11->capability_offset = 0x40; ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; - ivhd_11->pci_segment_group = 0x0000; + ivhd_11->pci_segment_group = nb_dev->bus->segment_group; ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; ivhd_11->iommu_attributes.perf_counters = (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; @@ -364,7 +364,7 @@ ivrs->ivhd.capability_offset = 0x40; ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; - ivrs->ivhd.pci_segment_group = 0x0000; + ivrs->ivhd.pci_segment_group = nb_dev->bus->segment_group; ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; /* Enable EFR if supported */ diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 140968c..605c4f5 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -218,7 +218,7 @@ ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd_40->iommu_base_low = ivhd->iommu_base_low; ivhd_40->iommu_base_high = ivhd->iommu_base_high; - ivhd_40->pci_segment_group = 0x0000; + ivhd_40->pci_segment_group = nb_dev->bus->segment_group; ivhd_40->iommu_info = ivhd->iommu_info; /* For type 40h bits 31:28 and 12:0 are reserved */ ivhd_40->iommu_attributes = ivhd->iommu_feature_info & 0xfffe000; @@ -275,7 +275,7 @@ ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); ivhd_11->iommu_base_low = ivhd->iommu_base_low; ivhd_11->iommu_base_high = ivhd->iommu_base_high; - ivhd_11->pci_segment_group = 0x0000; + ivhd_11->pci_segment_group = nb_dev->bus->segment_group; ivhd_11->iommu_info = ivhd->iommu_info; ivhd11_attr_ptr = (ivhd11_iommu_attr_t *)&ivhd->iommu_feature_info; ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; @@ -365,7 +365,7 @@ ivhd->flags |= ((mmio_x18_value & MMIO_CTRL_HT_TUN_EN) ? IVHD_FLAG_HT_TUN_EN : 0); - ivhd->pci_segment_group = 0x0000; + ivhd->pci_segment_group = nb_dev->bus->segment_group; ivhd->iommu_info = pci_read_config16(iommu_dev, ivhd->capability_offset + 0x10) & 0x1F; diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index c2f1406..f613513 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -21,12 +21,6 @@ return; } - /* TODO: Implement support for more than one PCI segment group in coreboot */ - if (segment_group) { - printk(BIOS_ERR, "coreboot currently only supports one PCI segment group.\n"); - return; - } - /* TODO: Check if bus >= CONFIG_ECAM_MMCONF_BUS_NUMBER and return in that case */ /* Make sure to not report more than CONFIG_ECAM_MMCONF_BUS_NUMBER PCI buses */ @@ -38,6 +32,7 @@ domain->link_list->subordinate = bus; /* Tell allocator about maximum PCI bus number in domain */ domain->link_list->max_subordinate = limit; + domain->link_list->segment_group = segment_group; pci_host_bridge_scan_bus(domain); } @@ -251,7 +246,7 @@ acpigen_resource_producer_bus_number(domain->link_list->secondary, domain->link_list->max_subordinate); - if (domain->link_list->secondary == 0) { + if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) { /* ACPI 6.4.2.5 I/O Port Descriptor */ acpigen_write_io16(PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_LAST_PORT, 1, PCI_IO_CONFIG_PORT_COUNT, 1); @@ -287,7 +282,7 @@ acpigen_write_resourcetemplate_footer(); - acpigen_write_SEG(0); + acpigen_write_SEG(domain->link_list->segment_group); acpigen_write_BBN(domain->link_list->secondary); /* Scope */ diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index f21cad5..dc37450 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -18,7 +18,7 @@ amd_pci_domain_read_resources(domain); // We only want to add the DRAM memory map once - if (domain->link_list->secondary == 0) { + if (domain->link_list->secondary == 0 && domain->link_list->segment_group == 0) { /* 0x1000 is a large enough first index to be sure to not overlap with the resources added by amd_pci_domain_read_resources */ add_opensil_memmap(domain, 0x1000); -- To view, visit https://review.coreboot.org/c/coreboot/+/79927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied3313c41896362dd989ee2ab1b1bcdced840aa8 Gerrit-Change-Number: 79927 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: lib/smbios: rename segment group parameter of smbios_write_type41
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79926?usp=email ) Change subject: lib/smbios: rename segment group parameter of smbios_write_type41 ...................................................................... lib/smbios: rename segment group parameter of smbios_write_type41 Rename the segment group parameter of smbios_write_type41 from 'segment' to 'segment_group' to be in line with the PCI specification. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e --- M src/include/smbios.h M src/lib/smbios.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/79926/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index f821980..d4ae662 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -41,7 +41,7 @@ const u64 base_addr, const u8 base_modifier, const u8 irq); int smbios_write_type41(unsigned long *current, int *handle, - const char *name, u8 instance, u16 segment, + const char *name, u8 instance, u16 segment_group, u8 bus, u8 device, u8 function, u8 device_type); enum smbios_temp_location; enum smbios_temp_status; diff --git a/src/lib/smbios.c b/src/lib/smbios.c index fb68b4f..12fbdfa 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -971,7 +971,7 @@ } int smbios_write_type41(unsigned long *current, int *handle, - const char *name, u8 instance, u16 segment, + const char *name, u8 instance, u16 segment_group, u8 bus, u8 device, u8 function, u8 device_type) { struct smbios_type41 *t = smbios_carve_table(*current, @@ -982,7 +982,7 @@ t->device_type = device_type; t->device_status = 1; t->device_type_instance = instance; - t->segment_group_number = segment; + t->segment_group_number = segment_group; t->bus_number = bus; t->device_number = device; t->function_number = function; @@ -1114,7 +1114,7 @@ return smbios_write_type41(current, handle, name, // name instance_id, // inst - 0, // segment + 0, // segment group dev->bus->secondary, //bus PCI_SLOT(dev->path.pci.devfn), // device PCI_FUNC(dev->path.pci.devfn), // func -- To view, visit https://review.coreboot.org/c/coreboot/+/79926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ca0ce8b6b3b0357df72bafa2b6069132d0937e Gerrit-Change-Number: 79926 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: lib/smbios: add segment_group parameter to smbios_write_type9
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79925?usp=email ) Change subject: lib/smbios: add segment_group parameter to smbios_write_type9 ...................................................................... lib/smbios: add segment_group parameter to smbios_write_type9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 --- M src/include/smbios.h M src/lib/smbios.c M src/mainboard/ocp/deltalake/ramstage.c 3 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/79925/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index f02b48b..f821980 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -32,7 +32,8 @@ const enum slot_data_bus_bandwidth bandwidth, const enum misc_slot_usage usage, const enum misc_slot_length length, - const u16 id, u8 slot_char1, u8 slot_char2, u8 bus, u8 dev_func); + const u16 id, u8 slot_char1, u8 slot_char2, + u8 segment_group, u8 bus, u8 dev_func); enum smbios_bmc_interface_type; int smbios_write_type38(unsigned long *current, int *handle, const enum smbios_bmc_interface_type interface_type, diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 3ef3c21..fb68b4f 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -639,7 +639,8 @@ const enum slot_data_bus_bandwidth bandwidth, const enum misc_slot_usage usage, const enum misc_slot_length length, - const u16 id, u8 slot_char1, u8 slot_char2, u8 bus, u8 dev_func) + const u16 id, u8 slot_char1, u8 slot_char2, + u8 segment_group, u8 bus, u8 dev_func) { struct smbios_type9 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_SLOTS, sizeof(*t), *handle); @@ -653,7 +654,7 @@ t->slot_length = length; t->slot_characteristics_1 = slot_char1; t->slot_characteristics_2 = slot_char2; - t->segment_group_number = 0; + t->segment_group_number = segment_group; t->bus_number = bus; t->device_function_number = dev_func; t->data_bus_width = SlotDataBusWidthOther; @@ -1166,6 +1167,7 @@ 0, 1, 0, + 0, dev->bus->secondary, dev->path.pci.devfn); } diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index d553392..c24d004 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -278,6 +278,7 @@ slot_id, characteristics_1, characteristics_2, + 0, /* segment group */ stack_busnos[slotinfo[index].stack], slotinfo[index].dev_func); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I48b393913913db8436f5cbca04d7411e68a53cf7 Gerrit-Change-Number: 79925 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/common/data_fabric/domain: write _SEG method in SSDT
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79924?usp=email ) Change subject: soc/amd/common/data_fabric/domain: write _SEG method in SSDT ...................................................................... soc/amd/common/data_fabric/domain: write _SEG method in SSDT As a preparation for the multi PCI segment group support, use acpigen_write_BBN to generate the _SEG method that returns the segment group number of the PCI root. Until the multi PCI segment group support is enabled in coreboot, it will always return 0. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a --- M src/soc/amd/common/block/data_fabric/domain.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/79924/1 diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 39f5790..c2f1406 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -287,6 +287,7 @@ acpigen_write_resourcetemplate_footer(); + acpigen_write_SEG(0); acpigen_write_BBN(domain->link_list->secondary); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2a812dcc564c5319385e9ad482d29b2984a71b8a Gerrit-Change-Number: 79924 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: acpi/acpigen: add acpigen_write_SEG for segment group number method
by Felix Held (Code Review) 12 Jan '24

12 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79923?usp=email ) Change subject: acpi/acpigen: add acpigen_write_SEG for segment group number method ...................................................................... acpi/acpigen: add acpigen_write_SEG for segment group number method Introduce acpigen_write_SEG to generate the ACPI method object that returns the PCI segment group number for a PCI(e) host bridge. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/79923/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 64ec734..257bd52 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -868,6 +868,17 @@ acpigen_pop_len(); } +void acpigen_write_SEG(uint8_t segment_group_number) +{ + /* + * Method (_SEG, 0, NotSerialized) { Return (status) } + */ + acpigen_write_method("_SEG", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_byte(segment_group_number); + acpigen_pop_len(); +} + void acpigen_write_LPI_package(u64 level, const struct acpi_lpi_state *states, u16 nentries) { /* diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index 7a5be51..d2e669f 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -436,6 +436,7 @@ void acpigen_write_STA(uint8_t status); void acpigen_write_STA_ext(const char *namestring); void acpigen_write_BBN(uint8_t base_bus_number); +void acpigen_write_SEG(uint8_t segment_group_number); void acpigen_write_TPC(const char *gnvs_tpc_limit); void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status); -- To view, visit https://review.coreboot.org/c/coreboot/+/79923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94837fdbe140ee1ff904ffd20bdab3e86f850774 Gerrit-Change-Number: 79923 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: libpayload: Make sure to install into the right DESTDIR
by Felix Singer (Code Review) 12 Jan '24

12 Jan '24

Attention is currently required from: Nico Huber. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79908?usp=email ) Change subject: libpayload: Make sure to install into the right DESTDIR ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61fa4aa0ecd0f81ee03ff89183e1b65e7875dea6 Gerrit-Change-Number: 79908 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 12 Jan 2024 00:03:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib/lzmadecode: Allow for 8 byte reads on 64bit
by Julius Werner (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Arthur Heymans. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70175?usp=email ) Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: Tested this on an Arm board (sc7180): noticed a small (not quite 2%) improvement for the LZMA decode times. -- To view, visit https://review.coreboot.org/c/coreboot/+/70175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa Gerrit-Change-Number: 70175 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 11 Jan 2024 22:45:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE option
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Attention is currently required from: Matt DeVillier, Michał Żygowski, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79893?usp=email ) Change subject: sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE option ...................................................................... Patch Set 1: (1 comment) File src/southbridge/amd/pi/hudson/fadt.c: https://review.coreboot.org/c/coreboot/+/79893/comment/935e1202_63ca5db7 : PS1, Line 38: fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; /* See table 5-10 */ : if (CONFIG(HUDSON_FADT_LEGACY_DEVICES)) : fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES; : if (CONFIG(HUDSON_FADT_8042)) : fadt->iapc_boot_arch |= ACPI_FADT_8042; > I'm curious whether the compiler creates code with one write. […] since those are all build-time constants, i'd expect the compiler to fully optimize this. and even if it won't there won't be much of a performance impact -- To view, visit https://review.coreboot.org/c/coreboot/+/79893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4ff85630c90fb2ae8c8826bbc9049a08668210d Gerrit-Change-Number: 79893 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 11 Jan 2024 22:37:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: cpu/x86/smi_trigger: use call_smm
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79828?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/x86/smi_trigger: use call_smm ...................................................................... cpu/x86/smi_trigger: use call_smm Use call_smm instead of writing the command number directly to the APMC SMI command IO port. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iefbdb3d17932d6db6a17b5771436ede220c714fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/79828 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/smi_trigger.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/cpu/x86/smi_trigger.c b/src/cpu/x86/smi_trigger.c index 5c63b9e..52c7247 100644 --- a/src/cpu/x86/smi_trigger.c +++ b/src/cpu/x86/smi_trigger.c @@ -3,6 +3,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <smm_call.h> #include <stdint.h> static void apmc_log(const char *fn, u8 cmd) @@ -38,7 +39,7 @@ apmc_log(__func__, cmd); /* Now raise the SMI. */ - outb(cmd, pm_acpi_smi_cmd_port()); + call_smm(cmd, 0, NULL); printk(BIOS_DEBUG, "APMC done.\n"); return CB_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/79828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefbdb3d17932d6db6a17b5771436ede220c714fb Gerrit-Change-Number: 79828 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: arch/x86/include/smm_call: improve documentation of call_smm
by Felix Held (Code Review) 11 Jan '24

11 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79834?usp=email ) Change subject: arch/x86/include/smm_call: improve documentation of call_smm ...................................................................... arch/x86/include/smm_call: improve documentation of call_smm Since the inline assembly code in call_smm doesn't make it exactly obvious how this function to call the APMC SMI handler works in detail, add a more detailed explanation as comment. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3566af191492ce00a3033335ff80e01c33e98e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79834 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/arch/x86/include/smm_call.h 1 file changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/arch/x86/include/smm_call.h b/src/arch/x86/include/smm_call.h index 66925c4..dc78039 100644 --- a/src/arch/x86/include/smm_call.h +++ b/src/arch/x86/include/smm_call.h @@ -4,7 +4,10 @@ #include <cpu/x86/smm.h> /* - * calls into SMM with the given cmd and subcmd in eax, and arg in ebx + * Call the APMC SMI handler that resides in SMM. First, the command and sub-command are stored + * in eax, and the argument pointer is stored in ebx, then the command byte is written to the + * APMC IO port to trigger the SMI. The APMC SMI handler then reads the command from the APMC + * IO port and the contents of eax and ebx from the SMM state save area. * * static inline because the resulting assembly is often smaller than * the call sequence due to constant folding. -- To view, visit https://review.coreboot.org/c/coreboot/+/79834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3566af191492ce00a3033335ff80e01c33e98e63 Gerrit-Change-Number: 79834 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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