coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

[L] Change in coreboot[main]: util/ifdtool: Add new cmdline to enable GPR0 protection
by Subrata Banik (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Stefan Reinauer, Subrata Banik. Hello Reka Norman, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80235?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/ifdtool: Add new cmdline to enable GPR0 protection ...................................................................... util/ifdtool: Add new cmdline to enable GPR0 protection This patch adds new cmdline `-E` support in the IFD Tool so that users (mostly factory) can enable GPR0 protection. Additionally, perform some code refactoring while adding support for enable GPR0 protection. BUG=b:270275115 TEST=Able to test GPR0 protection on google/rex and google/yahiko. > ifdtool -p mtl -E image.bin -O image.bin_lock ... Value at GPRD offset (64) is 0x83220004 --------- GPR0 Protected Range -------------- Start address = 0x00004000 End address = 0x00322fff ... GPR0 protection is now enabled Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 233 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/80235/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f Gerrit-Change-Number: 80235 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: soc/amd/common,genoa_poc/domain: rework check for 1st domain
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79996?usp=email ) Change subject: soc/amd/common,genoa_poc/domain: rework check for 1st domain ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad Gerrit-Change-Number: 79996 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 10:45:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[L] Change in coreboot[main]: soc/amd: factor out memmap from root_complex
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80272?usp=email ) Change subject: soc/amd: factor out memmap from root_complex ...................................................................... soc/amd: factor out memmap from root_complex Now that the SoC-specific memory map is reported on the domain device instead of the northbridge device, factor out the read_soc_memmap_resources function from root_complex.c to new memmap.c file. For now each SoC still has its own memmap.c file, but the plan is to eventually have a common implementation that works for all AMD family 17h+ SoCs. For that I'll still need to look closer into the differences between the FSP and the openSIL integration though. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9 --- M src/soc/amd/cezanne/Makefile.mk A src/soc/amd/cezanne/memmap.c M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/Makefile.mk A src/soc/amd/glinda/memmap.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/Makefile.mk A src/soc/amd/mendocino/memmap.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/Makefile.mk A src/soc/amd/phoenix/memmap.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/Makefile.mk A src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/root_complex.c 15 files changed, 494 insertions(+), 479 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/80272/1 diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 163f777..73be4aa 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -25,6 +25,7 @@ ramstage-y += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c diff --git a/src/soc/amd/cezanne/memmap.c b/src/soc/amd/cezanne/memmap.c new file mode 100644 index 0000000..6c8e932 --- /dev/null +++ b/src/soc/amd/cezanne/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 876f790..0fb086f 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -48,96 +42,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (86KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/glinda/Makefile.mk b/src/soc/amd/glinda/Makefile.mk index 4570e07..1211c45 100644 --- a/src/soc/amd/glinda/Makefile.mk +++ b/src/soc/amd/glinda/Makefile.mk @@ -29,6 +29,7 @@ ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c diff --git a/src/soc/amd/glinda/memmap.c b/src/soc/amd/glinda/memmap.c new file mode 100644 index 0000000..d347bae --- /dev/null +++ b/src/soc/amd/glinda/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 9d83f6f..36942bf 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Update for Glinda */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -63,96 +57,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/mendocino/Makefile.mk b/src/soc/amd/mendocino/Makefile.mk index cc44358..a72116e 100644 --- a/src/soc/amd/mendocino/Makefile.mk +++ b/src/soc/amd/mendocino/Makefile.mk @@ -27,6 +27,7 @@ ramstage-y += fsp_misc_data_hob.c ramstage-y += fsp_s_params.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += xhci.c ramstage-y += manifest.c diff --git a/src/soc/amd/mendocino/memmap.c b/src/soc/amd/mendocino/memmap.c new file mode 100644 index 0000000..d347bae --- /dev/null +++ b/src/soc/amd/mendocino/memmap.c @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 5561240..3247eb4 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Check if this is still correct */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <fsp/amd_misc_data.h> @@ -91,96 +85,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/phoenix/Makefile.mk b/src/soc/amd/phoenix/Makefile.mk index 26e9102..feb9b1a 100644 --- a/src/soc/amd/phoenix/Makefile.mk +++ b/src/soc/amd/phoenix/Makefile.mk @@ -31,6 +31,7 @@ ramstage-$(CONFIG_SOC_AMD_PHOENIX_FSP) += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += root_complex.c ramstage-y += soc_util.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/memmap.c b/src/soc/amd/phoenix/memmap.c new file mode 100644 index 0000000..432d850 --- /dev/null +++ b/src/soc/amd/phoenix/memmap.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/iomap.h> +#include <amdblocks/memmap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (30KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (120KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MiB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* + * top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. + */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + if (CONFIG(PLATFORM_USES_FSP2_0)) + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 4a657f8..4ce5f2a 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -3,17 +3,11 @@ /* TODO: Update for Phoenix */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> -#include <amdblocks/memmap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <soc/iomap.h> @@ -63,97 +57,6 @@ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (30KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (120KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MiB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* - * top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. - */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - if (CONFIG(PLATFORM_USES_FSP2_0)) - read_fsp_resources(dev, idx); -} - static void root_complex_init(struct device *dev) { register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); diff --git a/src/soc/amd/picasso/Makefile.mk b/src/soc/amd/picasso/Makefile.mk index 94d7f7bb..3fcd47f 100644 --- a/src/soc/amd/picasso/Makefile.mk +++ b/src/soc/amd/picasso/Makefile.mk @@ -26,6 +26,7 @@ ramstage-y += fsp_s_params.c ramstage-y += graphics.c ramstage-y += mca.c +ramstage-y += memmap.c ramstage-y += pcie_gpp.c ramstage-y += root_complex.c ramstage-y += sata.c diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c new file mode 100644 index 0000000..7ec7adf --- /dev/null +++ b/src/soc/amd/picasso/memmap.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/memmap.h> +#include <amdblocks/iomap.h> +#include <amdblocks/root_complex.h> +#include <arch/vga.h> +#include <cbmem.h> +#include <device/device.h> +#include <stdint.h> + +/* + * +--------------------------------+ + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * reserved_dram_end +--------------------------------+ + * | | + * | verstage (if reqd) | + * | (VERSTAGE_SIZE) | + * +--------------------------------+ VERSTAGE_ADDR + * | | + * | FSP-M | + * | (FSP_M_SIZE) | + * +--------------------------------+ FSP_M_ADDR + * | romstage | + * | (ROMSTAGE_SIZE) | + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 + * | bootblock | + * | (C_ENV_BOOTBLOCK_SIZE) | + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE + * | Unused hole | + * | (86KiB) | + * +--------------------------------+ + * | FMAP cache (FMAP_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 + * | Early Timestamp region (512B) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + * | Preram CBMEM console | + * | (PRERAM_CBMEM_CONSOLE_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + * | PSP shared (vboot workbuf) | + * | (PSP_SHAREDMEM_SIZE) | + * +--------------------------------+ PSP_SHAREDMEM_BASE + * | APOB (64KiB) | + * +--------------------------------+ PSP_APOB_DRAM_ADDRESS + * | Early BSP stack | + * | (EARLYRAM_BSP_STACK_SIZE) | + * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE + * | DRAM | + * +--------------------------------+ 0x100000 + * | Option ROM | + * +--------------------------------+ 0xc0000 + * | Legacy VGA | + * +--------------------------------+ 0xa0000 + * | DRAM | + * +--------------------------------+ 0x0 + */ +void read_soc_memmap_resources(struct device *dev, unsigned long *idx) +{ + uint32_t mem_usable = (uintptr_t)cbmem_top(); + + uintptr_t early_reserved_dram_start, early_reserved_dram_end; + const struct memmap_early_dram *e = memmap_get_early_dram_usage(); + + early_reserved_dram_start = e->base; + early_reserved_dram_end = e->base + e->size; + + /* 0x0 - 0x9ffff */ + ram_range(dev, (*idx)++, 0, 0xa0000); + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); + + /* 0xc0000 - 0xfffff: Option ROM */ + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); + + /* 1MB - bottom of DRAM reserved for early coreboot usage */ + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); + + /* DRAM reserved for early coreboot usage */ + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); + + /* top of DRAM consumed early - low top usable RAM + * cbmem_top() accounts for low UMA and TSEG if they are used. */ + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); + + /* Reserve fixed IOMMU MMIO region */ + mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); + + read_fsp_resources(dev, idx); +} diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 1e702ab..d4e8401 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -1,18 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpigen.h> -#include <amdblocks/acpi.h> #include <amdblocks/alib.h> #include <amdblocks/data_fabric.h> -#include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> -#include <amdblocks/iomap.h> #include <amdblocks/root_complex.h> #include <arch/ioapic.h> -#include <arch/vga.h> -#include <assert.h> -#include <cbmem.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <stdint.h> @@ -48,93 +41,6 @@ }, \ }, \ } -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END - * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE - * | Unused hole | - * | (86KiB) | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE - * | PSP shared (vboot workbuf) | - * | (PSP_SHAREDMEM_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -void read_soc_memmap_resources(struct device *dev, unsigned long *idx) -{ - uint32_t mem_usable = (uintptr_t)cbmem_top(); - - uintptr_t early_reserved_dram_start, early_reserved_dram_end; - const struct memmap_early_dram *e = memmap_get_early_dram_usage(); - - early_reserved_dram_start = e->base; - early_reserved_dram_end = e->base + e->size; - - /* 0x0 - 0x9ffff */ - ram_range(dev, (*idx)++, 0, 0xa0000); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); - - /* 0xc0000 - 0xfffff: Option ROM */ - reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); - - /* 1MB - bottom of DRAM reserved for early coreboot usage */ - ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); - - /* DRAM reserved for early coreboot usage */ - reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); - - /* top of DRAM consumed early - low top usable RAM - * cbmem_top() accounts for low UMA and TSEG if they are used. */ - ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); - - /* Reserve fixed IOMMU MMIO region */ - mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); - - read_fsp_resources(dev, idx); -} static void root_complex_init(struct device *dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd7659e9a55de9df24118b6d6c885a21dc6f14a9 Gerrit-Change-Number: 80272 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: soc/amd/phoenix/root_complex: make read_fsp_resources call conditional
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

1 0

[S] Change in coreboot[main]: soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

1 0

[S] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80269?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer ...................................................................... vc/amd/opensil/genoa_poc/memmap: pass resource index as pointer To make add_opensil_memmap match the other function that are directly or indirectly called by amd_pci_domain_read_resources, pass the resource index as a pointer instead of passing it by value and then returning the new resource index. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d --- M src/soc/amd/genoa_poc/domain.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h 3 files changed, 17 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/80269/1 diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index b34d2e3..711dfc3 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -15,7 +15,7 @@ void read_soc_memmap_resources(struct device *domain, unsigned long *idx) { - *idx = add_opensil_memmap(domain, *idx); + add_opensil_memmap(domain, idx); } static void genoa_domain_set_resources(struct device *domain) diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 8b54b5f..1e633d9 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -84,11 +84,11 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL); // This assumes holes are allocated -unsigned long add_opensil_memmap(struct device *dev, unsigned long idx) +void add_opensil_memmap(struct device *dev, unsigned long *idx) { - ram_from_to(dev, idx++, 0, 0xa0000); - mmio_from_to(dev, idx++, 0xa0000, 0xc0000); // legacy VGA - reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB); // Option ROM + ram_from_to(dev, (*idx)++, 0, 0xa0000); + mmio_from_to(dev, (*idx)++, 0xa0000, 0xc0000); // legacy VGA + reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); // Option ROM uint32_t mem_usable = (uintptr_t)cbmem_top(); uintptr_t early_reserved_dram_start, early_reserved_dram_end; @@ -98,33 +98,33 @@ early_reserved_dram_end = e->base + e->size; // 1MB - bottom of DRAM reserved for early coreboot usage - ram_from_to(dev, idx++, 1 * MiB, early_reserved_dram_start); + ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); // DRAM reserved for early coreboot usage - reserved_ram_from_to(dev, idx++, early_reserved_dram_start, + reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); // top of DRAM consumed early - low top usable RAM // cbmem_top() accounts for low UMA and TSEG if they are used. - ram_from_to(dev, idx++, early_reserved_dram_end, + ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); // Account for UMA and TSEG const uint32_t top_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 1 * MiB); if (mem_usable != top_mem) - reserved_ram_from_to(dev, idx++, mem_usable, top_mem); + reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem); - mmconf_resource(dev, idx++); + mmconf_resource(dev, (*idx)++); // Check if we're done if (top_of_mem <= 0x100000000) - return idx; + return; // Holes in upper DRAM // This assumes all the holes in upper DRAM are continuous get_hole_info(); if (hole_info == NULL) - return idx; + return; uint64_t lowest_upper_hole_base = top_of_mem; uint64_t highest_upper_hole_end = 0x100000000; for (int hole = 0; hole < n_holes; hole++) { @@ -135,16 +135,14 @@ lowest_upper_hole_base = MIN(lowest_upper_hole_base, hole_info[hole].Base); highest_upper_hole_end = MAX(highest_upper_hole_end, hole_info[hole].Base + hole_info[hole].Size); if (hole_info[hole].Type == UMA) - mmio_range(dev, idx++, hole_info[hole].Base, hole_info[hole].Size); + mmio_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); else - reserved_ram_range(dev, idx++, hole_info[hole].Base, hole_info[hole].Size); + reserved_ram_range(dev, (*idx)++, hole_info[hole].Base, hole_info[hole].Size); } - ram_from_to(dev, idx++, 0x100000000, lowest_upper_hole_base); + ram_from_to(dev, (*idx)++, 0x100000000, lowest_upper_hole_base); // Do we need this? if (top_of_mem > highest_upper_hole_end) - ram_from_to(dev, idx++, highest_upper_hole_end, top_of_mem); - - return idx; + ram_from_to(dev, (*idx)++, highest_upper_hole_end, top_of_mem); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index 77b3c4b..e225522 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -8,7 +8,7 @@ void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx -unsigned long add_opensil_memmap(struct device *dev, unsigned long idx); +void add_opensil_memmap(struct device *dev, unsigned long *idx); // Fill in FADT from openSIL void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); -- To view, visit https://review.coreboot.org/c/coreboot/+/80269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a17e488a01cc52b2dab5dd3e3d58bdf3acb554d Gerrit-Change-Number: 80269 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/amd: rework DRAM and fixed resource reporting
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

1 0

[S] Change in coreboot[main]: soc/amd/*/root_complex: use unsigned long for resource index
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

1 0

[S] Change in coreboot[main]: soc/amd/common/data_fabric/domain: use unsigned long for resource index
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

1 0

[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource index
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80265?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource index ...................................................................... vc/amd/opensil/genoa_poc/memmap: use unsigned long for resource index Use an unsigned long as resource index type instead of an int to match the data type used for the index in the resource struct and the functions to report the resources. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 --- M src/vendorcode/amd/opensil/genoa_poc/memmap.c M src/vendorcode/amd/opensil/genoa_poc/opensil.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/80265/1 diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 4e5b457..8b54b5f 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -84,7 +84,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL); // This assumes holes are allocated -int add_opensil_memmap(struct device *dev, int idx) +unsigned long add_opensil_memmap(struct device *dev, unsigned long idx) { ram_from_to(dev, idx++, 0, 0xa0000); mmio_from_to(dev, idx++, 0xa0000, 0xc0000); // legacy VGA diff --git a/src/vendorcode/amd/opensil/genoa_poc/opensil.h b/src/vendorcode/amd/opensil/genoa_poc/opensil.h index 473238d..77b3c4b 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/opensil.h +++ b/src/vendorcode/amd/opensil/genoa_poc/opensil.h @@ -8,7 +8,7 @@ void SIL_STATUS_report(const char *function, const int status); // Add the memory map to dev, starting at index idx, returns last use idx -int add_opensil_memmap(struct device *dev, int idx); +unsigned long add_opensil_memmap(struct device *dev, unsigned long idx); // Fill in FADT from openSIL void opensil_fill_fadt_io_ports(acpi_fadt_t *fadt); -- To view, visit https://review.coreboot.org/c/coreboot/+/80265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccc2e0556ce8688d933506e0db5cc4b83c66ac76 Gerrit-Change-Number: 80265 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2024