coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: drivers/intel/gma: Add missing parentheses to brightness ACPI
by Jonathon Hall (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Eric Lai, Felix Held, Felix Singer. Hello Eric Lai, Felix Held, Felix Singer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80260?usp=email to look at the new patch set (#2). Change subject: drivers/intel/gma: Add missing parentheses to brightness ACPI ...................................................................... drivers/intel/gma: Add missing parentheses to brightness ACPI Commit d25277666829 ("tree: Replace And(a,b) with ASL 2.0 syntax") replaced two instances of `And(var, mask) == 0` with `var & mask == 0`. This expression needs parentheses - `(var & mask) == 0`. Without parentheses, it is always false, since the masks are nonzero (`var & (mask == 0)`; `var & 0`; `0`). This caused brightness changes on Intel GMA to take longer than normal since the status was never checked. The brightness would change immediately, but another brightness change could not occur until the first change timed out. This was most noticeable in KDE, which waits for the brightness change to complete before accepting another brightness up/down keypress. Tapping brightness up/down repeatedly would take much longer to reach max/min brightness due to many presses being ignored. It is noticeable in GNOME as well but less obvious. Tapping brightness up/down repeatedly would handle all keypresses, but the display's actual brightness would lag behind and skip some intermediate steps. I tested both Librem 13v2 and Librem 14, as far as I know this would apply to all systems configuring brightness with Intel GMA. Test: Verify brightness keys respond quickly again on Librem 13v2 / 14. Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/80260/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Gerrit-Change-Number: 80260 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/gma: Add missing parentheses to brightness ACPI
by Jonathon Hall (Code Review) 31 Jan '24

31 Jan '24

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80260?usp=email ) Change subject: drivers/intel/gma: Add missing parentheses to brightness ACPI ...................................................................... drivers/intel/gma: Add missing parentheses to brightness ACPI Commit d2527766 "tree: Replace And(a,b) with ASL 2.0 syntax" replaced two instances of `And(var, mask) == 0` with `var & mask == 0`. This expression needs parentheses - `(var & mask) == 0`. Without parentheses, it is always false, since the masks are nonzero (`var & (mask == 0)`; `var & 0`; `0`). This caused brightness changes on Intel GMA to take longer than normal since the status was never checked. The brightness would change immediately, but another brightness change could not occur until the first change timed out. This was most noticeable in KDE, which waits for the brightness change to complete before accepting another brightness up/down keypress. Tapping brightness up/down repeatedly would take much longer to reach max/min brightness due to many presses being ignored. It is noticeable in GNOME as well but less obvious. Tapping brightness up/down repeatedly would handle all keypresses, but the display's actual brightness would lag behind and skip some intermediate steps. I tested both Librem 13v2 and Librem 14, as far as I know this would apply to all systems configuring brightness with Intel GMA. Test: Verify brightness keys respond quickly again on Librem 13v2 / 14. Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/drivers/intel/gma/acpi/configure_brightness_levels.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/80260/1 diff --git a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl index d6e417c..3a097e3 100644 --- a/src/drivers/intel/gma/acpi/configure_brightness_levels.asl +++ b/src/drivers/intel/gma/acpi/configure_brightness_levels.asl @@ -46,7 +46,7 @@ { Return (Ones) } - If (MBOX & 4 == 0) + If ((MBOX & 4) == 0) { Return (Ones) } @@ -74,7 +74,7 @@ While (Local0 > 0) { Sleep (1) - If (ASLC & 2 == 0) { + If ((ASLC & 2) == 0) { /* Request has been processed, check status: */ Local1 = (ASLC >> 12) & 3 If (Local1 == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I57895e8c654c83368b452d7adfe1856c0a0341fb Gerrit-Change-Number: 80260 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach more stacks
by Lean Sheng Tan (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80091?usp=email ) Change subject: soc/intel/xeon_sp: Attach more stacks ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 13:46:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach more stacks
by Lean Sheng Tan (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80091?usp=email ) Change subject: soc/intel/xeon_sp: Attach more stacks ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80091/comment/62579dd7_19027340 : PS7, Line 7: Attach more stacks Should this be more descriptive, like attach UBOX stacks? https://review.coreboot.org/c/coreboot/+/80091/comment/e9b31039_76a30914 : PS7, Line 10: attack attach? Please dont attack the stacks :D -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 13:46:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Sapphire Rapids FSP header path to Xeon SP
by Felix Singer (Code Review) 31 Jan '24

31 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80241?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: MAINTAINERS: Add Sapphire Rapids FSP header path to Xeon SP ...................................................................... MAINTAINERS: Add Sapphire Rapids FSP header path to Xeon SP Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80241 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/MAINTAINERS b/MAINTAINERS index 8b4f26d..d093071 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -948,6 +948,7 @@ F: src/soc/intel/xeon_sp/ F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ MEDIATEK SOCS M: Hung-Te Lin <hungte(a)chromium.org> -- To view, visit https://review.coreboot.org/c/coreboot/+/80241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Gerrit-Change-Number: 80241 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP
by Felix Singer (Code Review) 31 Jan '24

31 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80240?usp=email ) Change subject: MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP ...................................................................... MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80240 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/MAINTAINERS b/MAINTAINERS index 2648f36..8b4f26d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -941,6 +941,9 @@ M: Tim Chu <Tim.Chu(a)quantatw.com> M: Arthur Heymans <arthur(a)aheymans.xyz> M: Christian Walter <christian.walter(a)9elements.com> +M: Shuo Liu <shuo.liu(a)intel.com> +M: Patrick Rudolph <patrick.rudolph(a)9elements.com> +M: Lean Sheng Tan <sheng.tan(a)9elements.com> S: Supported F: src/soc/intel/xeon_sp/ F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP
by Felix Singer (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80240?usp=email ) Change subject: MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80240/comment/6b010d0a_48203d97 : PS2, Line 7: Update maintainers list for Xeon SP : > Acknowledged I'm just saying that nothing is set into stone. It's just a commit as any other, right? When multiple people are added it's fine to choose a rather common title and put the details into the description. So please let's not be too picky. -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 31 Jan 2024 13:42:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/phoenix/chip: make FSP-S call conditional
by Felix Held (Code Review) 31 Jan '24

31 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80242?usp=email ) Change subject: soc/amd/phoenix/chip: make FSP-S call conditional ...................................................................... soc/amd/phoenix/chip: make FSP-S call conditional Only call amd_fsp_silicon_init if PLATFORM_USES_FSP2_0 is selected in Kconfig. I'm not 100% sure about the data_fabric_set_mmio_np call yet, but since it doesn't depend on PLATFORM_USES_FSP2_0 to compile, I'll look into that one later. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80242 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/phoenix/chip.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index 72652ba..2291945 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -39,7 +39,8 @@ { default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables; - amd_fsp_silicon_init(); + if (CONFIG(PLATFORM_USES_FSP2_0)) + amd_fsp_silicon_init(); data_fabric_set_mmio_np(); -- To view, visit https://review.coreboot.org/c/coreboot/+/80242?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2666f1ac0f0354146ffe005b3ce99484defda7a8 Gerrit-Change-Number: 80242 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Config TCSS AUX according board_id
by Weimin Wu (Code Review) 31 Jan '24

31 Jan '24

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80259?usp=email ) Change subject: mb/google/nissa/var/anraggar: Config TCSS AUX according board_id ...................................................................... mb/google/nissa/var/anraggar: Config TCSS AUX according board_id EVT mini build (board_id = 2) change retimer IC. Need to reconfigure TCSS AUX connect to SOC directly. Perform compatibility processing based on board_id. BUG=b:none TEST=DP function of MB and DB workable Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb M src/mainboard/google/brya/variants/anraggar/variant.c 2 files changed, 34 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/80259/1 diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 9646f29..bc4f8e5 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -60,21 +60,6 @@ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" - # SOC Aux orientation override: - # This is a bitfield that corresponds to up to 4 TCSS ports. - # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. - # TcssAuxOri = 0100b - # Bit0 set to "0" indicates has retimer on USBC Port0, on the DB. - # Bit2 set to "1" indicates no retimer on USBC Port1, on the MB. - # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the - # motherboard to USBC connector - register "tcss_aux_ori" = "4" - - register "typec_aux_bias_pads[0]" = "{ - .pad_auxp_dc = GPP_E22, - .pad_auxn_dc = GPP_E23 - }" - # FIVR configurations for anraggar are disabled since the board doesn't have V1p05 and Vnn # bypass rails implemented. register "ext_fivr_settings" = "{ diff --git a/src/mainboard/google/brya/variants/anraggar/variant.c b/src/mainboard/google/brya/variants/anraggar/variant.c index 4221a5b..486e7f3 100644 --- a/src/mainboard/google/brya/variants/anraggar/variant.c +++ b/src/mainboard/google/brya/variants/anraggar/variant.c @@ -1,5 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <chip.h> +#include <soc/gpio_soc_defs.h> +#include <baseboard/variants.h> +#include <boardid.h> #include <fw_config.h> #include <sar.h> @@ -7,3 +11,33 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); } + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + /* + * SOC Aux orientation override: + * This is a bitfield that corresponds to up to 4 TCSS ports. + * Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + * Bit0, Bit2 set to "0" indicates has retimer on TCSS Port. + * Bit0, Bit2 set to "1" indicates no retimer on TCSS Port. + * Bit1, Bit3 set to "0" indicates Aux lines are not swapped on TCSS Port. + * Bit1, Bit3 set to "1" indicates Aux lines are swapped on TCSS Port. + */ + + switch (board_id()){ + case 0: /* proto */ + case 1: /* evt */ + config->tcss_aux_ori = 4; + config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22; + config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23; + break; + case 2: /* evt mini build (DB TCSS AUX connect to SOC directly) */ + config->tcss_aux_ori = 5; + config->typec_aux_bias_pads[1].pad_auxp_dc = GPP_E22; + config->typec_aux_bias_pads[1].pad_auxn_dc = GPP_E23; + config->typec_aux_bias_pads[0].pad_auxp_dc = GPP_A19; + config->typec_aux_bias_pads[0].pad_auxn_dc = GPP_A20; + break; + default: + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/80259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53974ec7444912a63d0fe0a9303c9e5d6941f68d Gerrit-Change-Number: 80259 Gerrit-PatchSet: 1 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switching
by Tyler Wang (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jack Lai, Jakub Czapiga, Kapil Porwal, Mac Chiang, Subrata Banik, Tarun. Tyler Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80215?usp=email ) Change subject: mb/google/rex/var/karis: Follow rex0 CNVi/PCIe switching ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/80215?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id23a2cfe0639f2d423980db9badc16c1477434d1 Gerrit-Change-Number: 80215 Gerrit-PatchSet: 5 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jack Lai <jack.lai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Jack Lai <jack.lai(a)intel.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 13:29:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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