coreboot-gerrit January 2024

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[S] Change in coreboot[main]: acpi/acpi: Pass struct device to acpi_create_srat_gia_pci
by Patrick Rudolph (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Johnny Lin, Lance Zhao, Tim Chu, Tim Wawrzynczak. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80258?usp=email ) Change subject: acpi/acpi: Pass struct device to acpi_create_srat_gia_pci ...................................................................... acpi/acpi: Pass struct device to acpi_create_srat_gia_pci Instead of S:B:D:F numbers pass the struct device to acpi_create_srat_gia_pci and let it extract the information needed. This also adds support for PCI multi segment groups. Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/xeon_sp/uncore_acpi_cxl.c 3 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/80258/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 6bf452e..98c8ecd 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -352,17 +352,22 @@ } int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain, - u16 seg, u8 bus, u8 dev, u8 func, u32 flags) + struct device *dev, u32 flags) { + /* Only handle PCI devices. */ + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + gia->type = ACPI_SRAT_STRUCTURE_GIA; gia->length = sizeof(acpi_srat_gia_t); gia->proximity_domain = proximity_domain; gia->dev_handle_type = ACPI_SRAT_GIA_DEV_HANDLE_PCI; /* First two bytes has segment number */ - memcpy(gia->dev_handle, &seg, 2); - gia->dev_handle[2] = bus; /* Byte 2 has bus number */ + gia->dev_handle[0] = dev->upstream->segment_group; + gia->dev_handle[1] = 0; + gia->dev_handle[2] = dev->upstream->secondary; /* Byte 2 has bus number */ /* Byte 3 has bits 7:3 for dev, bits 2:0 for func */ - gia->dev_handle[3] = PCI_SLOT(dev) | PCI_FUNC(func); + gia->dev_handle[3] = dev->path.pci.devfn; gia->flags = flags; return gia->length; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d5f4008..c39683e 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1782,7 +1782,7 @@ * and flag, create Generic Initiator Affinity structure in SRAT. */ int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain, - u16 seg, u8 bus, u8 dev, u8 func, u32 flags); + struct device *dev, u32 flags); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); diff --git a/src/soc/intel/xeon_sp/uncore_acpi_cxl.c b/src/soc/intel/xeon_sp/uncore_acpi_cxl.c index 6785937..40a5f12 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi_cxl.c +++ b/src/soc/intel/xeon_sp/uncore_acpi_cxl.c @@ -12,19 +12,14 @@ * In the pds (Proximity Domains structure), Generic Initiator domains * are after processor domains. */ - uint16_t seg = 0; - uint8_t bus, dev, func; uint32_t base, size; for (uint8_t i = soc_get_num_cpus(); i < pds.num_pds; i++) { - bus = PCI_BDF(pds.pds[i].dev) >> 20; - dev = (PCI_BDF(pds.pds[i].dev) >> 15) & 0x1f; - func = (PCI_BDF(pds.pds[i].dev) >> 12) & 0x07; - printk(BIOS_DEBUG, - "adding srat GIA ID: %d, seg: 0x%x, bus: 0x%x, dev: 0x%x, func: 0x%x\n", - i, seg, bus, dev, func); + if (!pds.pds[i].dev) + continue; + + printk(BIOS_DEBUG, "adding srat GIA ID: %d, dev: %s\n", i, dev_path(pds.pds[i].dev)); /* flags: 1 (enabled) */ - current += acpi_create_srat_gia_pci((acpi_srat_gia_t *)current, i, seg, bus, - dev, func, 1); + current += acpi_create_srat_gia_pci((acpi_srat_gia_t *)current, i, pds.pds[i].dev, 1); base = pds.pds[i].base << 16; size = pds.pds[i].size << 16; printk(BIOS_DEBUG, -- To view, visit https://review.coreboot.org/c/coreboot/+/80258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iafe32e98f0c85f14347695ccaa0225e43fad99e7 Gerrit-Change-Number: 80258 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp/numa: Store pointer to device
by Patrick Rudolph (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80257?usp=email ) Change subject: soc/intel/xeon_sp/numa: Store pointer to device ...................................................................... soc/intel/xeon_sp/numa: Store pointer to device Instead of a BDF number store a pointer to the device itself. Change-Id: I3fef93c5e54c8af792102bcd25364c43b554a5f0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/numa.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore_acpi_cxl.c 5 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/80257/1 diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index 48141c7..6aaf172 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -41,7 +41,7 @@ /* * Below fields are set to 0 for processor domains. */ - uint32_t device_handle; /* This holds PCIe device segment, BDF info */ + struct device *dev; uint32_t base; /* Memory region base address in the unit of 64MB */ uint32_t size; /* Memory region size in the unit of 64MB */ }; diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 2b529b9..d57b240 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -196,7 +196,7 @@ for (i = 0; i < pds.num_pds; i++) { if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) continue; - ep_bus = pds.pds[i].device_handle >> 20; + ep_bus = PCI_BDF(pds.pds[i].dev) >> 20; if (ep_bus == ecrc_bus + 1) break; } diff --git a/src/soc/intel/xeon_sp/spr/numa.c b/src/soc/intel/xeon_sp/spr/numa.c index ef1c153..169f4f8 100644 --- a/src/soc/intel/xeon_sp/spr/numa.c +++ b/src/soc/intel/xeon_sp/spr/numa.c @@ -19,7 +19,7 @@ printk(BIOS_DEBUG, "\tproximity domain %d:\n", i); printk(BIOS_DEBUG, "\t\ttype:%d\n", pds.pds[i].pd_type); printk(BIOS_DEBUG, "\t\tsocket_bitmap:0x%x\n", pds.pds[i].socket_bitmap); - printk(BIOS_DEBUG, "\t\tdevice_handle:0x%x\n", pds.pds[i].device_handle); + printk(BIOS_DEBUG, "\t\tdevice:%s\n", pds.pds[i].dev ? dev_path(pds.pds[i].dev) : ""); printk(BIOS_DEBUG, "\t\tbase(64MB):0x%x\n", pds.pds[i].base); printk(BIOS_DEBUG, "\t\tsize(64MB):0x%x\n", pds.pds[i].size); } @@ -85,7 +85,7 @@ pds.pds[i].base = node.Address; pds.pds[i].size = node.Size; dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); - pds.pds[i].device_handle = PCI_BDF(dev); + pds.pds[i].dev = dev; pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 07515e9..970b641 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -91,7 +91,7 @@ if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) continue; - uint32_t bus = pds.pds[i].device_handle >> 20; + uint32_t bus = PCI_BDF(pds.pds[i].dev) >> 20; if (bus >= res->BusBase && bus <= res->BusLimit) return true; } diff --git a/src/soc/intel/xeon_sp/uncore_acpi_cxl.c b/src/soc/intel/xeon_sp/uncore_acpi_cxl.c index de776eb..6785937 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi_cxl.c +++ b/src/soc/intel/xeon_sp/uncore_acpi_cxl.c @@ -16,9 +16,9 @@ uint8_t bus, dev, func; uint32_t base, size; for (uint8_t i = soc_get_num_cpus(); i < pds.num_pds; i++) { - bus = pds.pds[i].device_handle >> 20; - dev = (pds.pds[i].device_handle >> 15) & 0x1f; - func = (pds.pds[i].device_handle >> 12) & 0x07; + bus = PCI_BDF(pds.pds[i].dev) >> 20; + dev = (PCI_BDF(pds.pds[i].dev) >> 15) & 0x1f; + func = (PCI_BDF(pds.pds[i].dev) >> 12) & 0x07; printk(BIOS_DEBUG, "adding srat GIA ID: %d, seg: 0x%x, bus: 0x%x, dev: 0x%x, func: 0x%x\n", i, seg, bus, dev, func); -- To view, visit https://review.coreboot.org/c/coreboot/+/80257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fef93c5e54c8af792102bcd25364c43b554a5f0 Gerrit-Change-Number: 80257 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Initial support for PCI multi segment groups
by Patrick Rudolph (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Naresh Solanki, Nill Ge, Shuo Liu, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79878?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Initial support for PCI multi segment groups ...................................................................... soc/intel/xeon_sp: Initial support for PCI multi segment groups Add PCI enumeration support by reading the PCIeSegment reported in the FSP HOB and add it when creating the PCI domain for each stack. The PCI enumeration will be able to scan the additional PCI segment groups and properly handle those devices. Code that still hardcodes B:D:F numbers will not work when PCI multi segment support is enabled and need to be updated in future commits. In addition ACPI code generation needs to take PCI segment groups into account. Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/spr/ioat.c 3 files changed, 48 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79878/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Annie Chen <chen.annieet(a)inventec.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Attach more stacks
by Patrick Rudolph (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Lean Sheng Tan, Nico Huber, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80091?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp: Attach more stacks ...................................................................... soc/intel/xeon_sp: Attach more stacks Attach UBOX stacks as well and thus rename the function to attack_stacks. In order to use PCI drivers for UBOX devices, locating UBOX devices by vendor and device IDs and replacing device access by specifying S:B:D:F numbers, add a PCI domain for the UBOX stacks and let the PCI enumerator index all devices. Since there are no PCI BARs on the UBOX bus the PCI locator doesn't have to assign resources on those buses. Once all PCI devices on the UBOX stack can be located without knowing their UBOX bus number and PCI segment the Xeon-SP code can fully enable the multi PCI segment group support. Test: ibm/sbp1 (4S) is able to find all PCU devices by PCI ID. Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c 5 files changed, 91 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/80091/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80091?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9d52dd117364a42de1c73d39cc86dafeaf2678 Gerrit-Change-Number: 80091 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Michał Żygowski, Nico Huber, Patrick Rudolph. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77338?usp=email ) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... Patch Set 12: (5 comments) File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/74fc411f_6bd48d71 : PS10, Line 709: pciexp_configure_max_payload > Finally figured out how it should work. […] This is done. Also, when the scan bus on root port is finished, the root port's current max payload size in synced to all downstream devices of this port. File src/device/pciexp_device.c: https://review.coreboot.org/c/coreboot/+/77338/comment/230f1e58_6c12c4cf : PS11, Line 594: root_devcap > The name no longer describes what this variable holds. Changed the variable names to child and parent where appropriate. https://review.coreboot.org/c/coreboot/+/77338/comment/7d084851_a74a2dc3 : PS11, Line 598: awlays > always Fixed https://review.coreboot.org/c/coreboot/+/77338/comment/a98d6e6b_54f5db11 : PS11, Line 608: & PCI_EXP_DEVCAP_PAYLOAD > No need to mask it here, it was already masked right after reading. Fixed https://review.coreboot.org/c/coreboot/+/77338/comment/144cfb83_69355013 : PS11, Line 630: root->max_payload_set = 1; > Exactly. […] Ad.2. Second walk implemented in patchset 12 -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 31 Jan 2024 12:16:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: device/pciexp_device.c: Fix setting Max Payload Size
by Michał Żygowski (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Krystian Hebel, Kyösti Mälkki, Nico Huber, Patrick Rudolph. Hello Angel Pons, Arthur Heymans, Felix Held, Kyösti Mälkki, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77338?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/pciexp_device.c: Fix setting Max Payload Size ...................................................................... device/pciexp_device.c: Fix setting Max Payload Size Current implementation assumes that the endpoint device is connected directly to the PCIe Root Port, which does not always have to be true. In a case where there is a PCIe switch between the endpoint and the root port, the Max Payload Size capability may differ across the devices in the chain and coreboot will not set a correct Max Payload Size. This results in a PCIe device malfunction in pre-OS environment, e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE fails to obtain the DHCP configuration. Fix this by traversing the topology and programming the highest common Max Payload Size in the given PCIe device chain during enumeration. Once finished, the root port has the highest common Max Payload Size supported by all the devices in the chain. So at the end of roott port bus scan, propagate the root port's Max Payload Size to all downstream devices to keep Max Payload Size in sync within the whole chain. TEST=Perform successful dhcp command in iPXE on the NIC connected to the PCIe root port via ASMedia ASM1806 PCIe switch and again on the NIC connected directly to the PCIe root port. Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/device/pciexp_device.c M src/include/device/device.h 2 files changed, 149 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77338/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/77338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24386dc208363b7d94fea46dec25c231a3968225 Gerrit-Change-Number: 77338 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/common/block: Add support for watchdog
by Marek Maślanka (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Jakub Czapiga, Michał Żygowski, Subrata Banik. Marek Maślanka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79909?usp=email ) Change subject: soc/intel/common/block: Add support for watchdog ...................................................................... Patch Set 13: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/60029fb0_71be61e5 : PS12, Line 468: entry->action = ACPI_WDAT_SET_RUNNING_STATE; : entry->instruction = ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER; : entry->mask = 0x01; : entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; : entry->register_region.addrl = tcobase + TCO1_CNT; : entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; : entry->register_region.bit_offset = 11; > > I would prefer to keep it consistent with filling in other entries instead of creating separate fu […] By "consistent with filling in other entries" I meant that you want to have a fill_wdat_entry function that will only fill those two entries ACPI_WDAT_SET_RUNNING_STATE and ACPI_WDAT_SET_STOPPED_STATE, and leave the rest unchanged (fills it directly in the acpi_soc_fill_wdat function). Anyway, notice that the entries differ not only in `action` type, but also in other fields, which will require function with many parameter. Maybe it will be better to introduce separate functions for related entries/actions like, "fill_wdat_run_status_entry", "fill_wdat_boot_status_entry", "fill_wdat_ping_entry" and "fill_wdat_timeout_entry". In that case functions will have a small amount of parameters. File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79909/comment/20f72884_55c699e4 : PS13, Line 396: rightmost_bit_offset > i'm unable to follow which right most bit u r considering ? may be a little meaningful name with the […] The only thing that comes to mind to make the name more descriptive is to change it to `find_rightmost_set_bit_offset` -- To view, visit https://review.coreboot.org/c/coreboot/+/79909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf7971f8407920a553fd91d2ed04193c882e08f1 Gerrit-Change-Number: 79909 Gerrit-PatchSet: 13 Gerrit-Owner: Marek Maślanka <mmaslanka(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Comment-Date: Wed, 31 Jan 2024 11:30:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marek Maślanka <mmaslanka(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP
by Shuo Liu (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Lean Sheng Tan, Patrick Rudolph, Paul Menzel. Hello Arthur Heymans, Felix Held, Felix Singer, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80240?usp=email to look at the new patch set (#6). Change subject: MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP ...................................................................... MAINTAINERS: Add Shuo, Patrick and Lean Sheng for Xeon SP Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M MAINTAINERS 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/80240/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: MAINTAINERS: Add Shuo, Patrick and Sheng for Xeon SP
by Shuo Liu (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Lean Sheng Tan, Patrick Rudolph, Paul Menzel. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80240?usp=email ) Change subject: MAINTAINERS: Add Shuo, Patrick and Sheng for Xeon SP ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80240/comment/0fe920e9_56413f0b : PS2, Line 7: Update maintainers list for Xeon SP : > it is always this way as Paul suggested: […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide3aa87fca69be6b0f1ffe0b18d7ffb410e5c563 Gerrit-Change-Number: 80240 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 31 Jan 2024 11:13:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Sapphire Rapids FSP header path to Xeon SP
by Shuo Liu (Code Review) 31 Jan '24

31 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Patrick Rudolph, Paul Menzel. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80241?usp=email ) Change subject: MAINTAINERS: Add Sapphire Rapids FSP header path to Xeon SP ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80241/comment/5f7c561f_bada4a48 : PS2, Line 7: headers > header path Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80241?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20ad4bc325d5cfe7a9d5f8b349eeea3d6218452b Gerrit-Change-Number: 80241 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 31 Jan 2024 11:13:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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