Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80046?usp=email )
Change subject: mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into references
......................................................................
mb/hp/snb_ivb_desktops: Convert remaining PCI numbers into references
Change-Id: I31e348ba5954bc463f43e769ddb4aed413faf193
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
2 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/80046/1
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
index 55bdaac..3634b90 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb
@@ -3,16 +3,16 @@
chip northbridge/intel/sandybridge
device domain 0 on
subsystemid 0x103c 0x1791 inherit
- device pci 06.0 on end # Extra x4 port on north bridge
+ device ref peg60 on end # Extra x4 port on north bridge
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0x3f"
- device pci 1c.1 on end # PCIe Port #2
- device pci 1c.2 on end # PCIe Port #3
- device pci 1c.3 on end # PCIe Port #4
- device pci 1c.5 on end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 on end # PCIe Port #8
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 on end # PCIe Port #7
+ device ref pcie_rp8 on end # PCIe Port #8
end
end
end
diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
index c31bf33..8b827f8 100644
--- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
+++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb
@@ -6,7 +6,7 @@
chip southbridge/intel/bd82x6x
register "sata_port_map" = "0xf"
- device pci 1c.4 on end # dummy setting
+ device ref pcie_rp5 on end # dummy setting
end
end
end
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Gerrit-Change-Id: I31e348ba5954bc463f43e769ddb4aed413faf193
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 )
Change subject: sb/intel/bd82x6x: Rework PCH ID cache
......................................................................
sb/intel/bd82x6x: Rework PCH ID cache
Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.
Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/southbridge/intel/bd82x6x/common.c
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1
diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
index 7480174..0094db6 100644
--- a/src/southbridge/intel/bd82x6x/common.c
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -13,9 +13,9 @@
int pch_silicon_revision(void)
{
- static int pch_revision_id = -1;
+ static int pch_revision_id = 0;
- if (pch_revision_id < 0)
+ if (!pch_revision_id)
pch_revision_id = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
return pch_revision_id;
@@ -23,9 +23,9 @@
int pch_silicon_type(void)
{
- static int pch_type = -1;
+ static int pch_type = 0;
- if (pch_type < 0)
+ if (!pch_type)
pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
return pch_type;
--
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Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74442?usp=email )
Change subject: Update fsp submodule to upstream master
......................................................................
Abandoned
Out of date and submodule pointer got updated by another patch in the meantime.
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Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80022?usp=email )
Change subject: mb/siemens/chili: Use chipset dt reference names
......................................................................
Patch Set 2: Code-Review+2
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Daniel Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79976?usp=email )
Change subject: mb/google/dedede/var/galtic: Correct name for mem-part K4U6E3S4AA-MGCR
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Hi Googler,
Sorry to push for review. Due to schedule and we have also 1 CL(for b/320137193) that needs to implement after this CL is emerged.
Please kindly help to submit the CL if no concern.
Thanks.
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Felix Singer has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/80045?usp=email )
Change subject: 3rdparty/arm-trusted-firmware: Update submodule to upstream master
......................................................................
3rdparty/arm-trusted-firmware: Update submodule to upstream master
Updating from commit id e7486343d:
2023-11-28 22:48:16 +0100 - (Merge changes from topic "xlnx_fitimage_check" into integration)
to commit id 23d6774ab:
2024-01-16 09:47:43 +0100 - (Merge "feat(qemu-sbsa): mpidr needs to be present" into integration)
This brings in 150 new commits.
Change-Id: I4aefd60dcd785934286eb8f7b0defd61c73e78f7
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M 3rdparty/arm-trusted-firmware
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/80045/2
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