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Change subject: mb/starlabs/starbook/cml: Use chipset dt reference names
......................................................................
Patch Set 1: Code-Review+2
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Change subject: intel skl mainboards: Move PcieRpEnable option below dt entries
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS6:
I'm sorry but I don't really understand the motivation behing sliding this patch before CB:79917. Making the PcieRpEnable entries more readable by moving them under the devices to be later removed is a no-op. IMO, it's not such a cognitive load to scroll a few lines under and check which RPs corresponding to the PcieRpEnable are on. If any remain after the removal, they can be moved later.
File src/mainboard/51nb/x210/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79958/comment/872198d3_6761b43a :
PS6, Line 59: register "PcieRpEnable[2]" = "1" # Ethernet controller
This will just create a merge conflict with CB:79917 because e.g. on their side the comment is preserved. I'd wait for that patch to be merged and then make any style changes if that is your concern.
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Change subject: mb/google/brox: Enable HDA Codec ALC256
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79723/comment/3e8591f7_cbb4a6e5 :
PS5, Line 7: Codec-ALC256
> Remove the hyphen?
Done
https://review.coreboot.org/c/coreboot/+/79723/comment/31e9a997_a6958d9a :
PS5, Line 9: ALC 256
> Remove the space?
Done
https://review.coreboot.org/c/coreboot/+/79723/comment/9410e895_401cad0e :
PS5, Line 9: Add verb table for the same.
> How did you create this?
ALC256 file based on which the verb table generated is added in cross bug.
https://review.coreboot.org/c/coreboot/+/79723/comment/12b15eae_016c5ec4 :
PS5, Line 11:
> Please document the datasheet name and revision.
Done
https://review.coreboot.org/c/coreboot/+/79723/comment/883d30e0_ccda2d10 :
PS5, Line 14: To verify HDA on Brox
> Does that mean, you are going to test it?
Yes, It needs to be tested based on the board availability.
Shelly is planning to test it next week.
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Hello Paul Menzel, Shelley Chen, Vamshi Krishna Gopal, Vamshi Krishna Gopal, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79723?usp=email
to look at the new patch set (#6).
Change subject: mb/google/brox: Enable HDA Codec ALC256
......................................................................
mb/google/brox: Enable HDA Codec ALC256
On Brox, HDA Codec used is ALC256. Add verb table for the same. Also,
add the related device tree changes for HDA related registers.
Realtek High Definition Audio Configuration-
Version : 5.0.3.1
BUG=b:317398558
BRANCH=None
TEST=To verify HDA on Brox
Change-Id: I1edd5aee053debe39b34048266703031c088cd00
Signed-off-by: Poornima Tom <poornima.tom(a)intel.com>
---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/Makefile.inc
A src/mainboard/google/brox/hda_verb.c
M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
4 files changed, 123 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/79723/6
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79415?usp=email )
Change subject: mb/intel/adlrvp: Add Realtek ALC256 audio verb table
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> Good Suggestion Subrata, Yes ALC256 verb table is generic. Verb table can be design agnostic.
perfect. if u wish to do this as part of this patch train then I don't mind. Otherwise if u want to land this CL as is and then push a common CL then leverage the common cl from adlrvp?
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80056?usp=email )
Change subject: mb/purism/librem_cnl: Use chipset dt reference names
......................................................................
mb/purism/librem_cnl: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/purism/librem_cnl/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
3 files changed, 65 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/80056/1
diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb
index ff21977..3d26b09 100644
--- a/src/mainboard/purism/librem_cnl/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/devicetree.cb
@@ -44,58 +44,58 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on # SA Thermal device
+ device ref system_agent on end
+ device ref igpu on end
+ device ref dptf on
register "Device4Enable" = "1"
end
- device pci 12.0 on end # Thermal Subsystem
- device pci 13.0 off end # Integrated Sensor Hub
- device pci 14.0 on end # USB xHC
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on end # SATA
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 off end # PCI Express Port 9
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 off end # PCI Express Port 13
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on end # LPC Bridge
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
+ device ref thermal on end
+ device ref ish off end
+ device ref xhci on end
+ device ref xdci off end
+ device ref i2c0 off end
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 off end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref heci4 off end
+ device ref sata on end
+ device ref i2c4 off end
+ device ref i2c5 off end
+ device ref uart2 off end
+ device ref emmc off end
+ device ref pcie_rp1 off end
+ device ref pcie_rp2 off end
+ device ref pcie_rp3 off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref pcie_rp9 off end
+ device ref pcie_rp10 off end
+ device ref pcie_rp11 off end
+ device ref pcie_rp12 off end
+ device ref pcie_rp13 off end
+ device ref pcie_rp14 off end
+ device ref pcie_rp15 off end
+ device ref pcie_rp16 off end
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on end
+ device ref p2sb off end
+ device ref pmc hidden end
+ device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ device ref smbus on end
+ device ref fast_spi on end
+ device ref gbe off end
end
end
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
index ef35ac0..b3fd862 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
@@ -24,7 +24,7 @@
# Actual device tree
device domain 0 on
- device pci 02.0 on # Integrated Graphics Device
+ device ref igpu on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
register "panel_cfg" = "{
.up_delay_ms = 200,
@@ -35,7 +35,7 @@
.backlight_off_delay_ms = 1,
}"
end
- device pci 14.0 on # USB xHCI
+ device ref xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -131,8 +131,8 @@
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 15.0 on # I2C #0
+ device ref xdci off end
+ device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""HTIX5288""
register "generic.name" = ""TPD0""
@@ -142,7 +142,7 @@
device i2c 2c on end
end
end
- device pci 17.0 on # SATA
+ device ref sata on
register "satapwroptimize" = "1"
register "SataSalpSupport" = "1"
# Port 2 (M.2 / inner)
@@ -152,7 +152,7 @@
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
end
- device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN)
+ device ref pcie_rp7 on # x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[6]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
@@ -161,13 +161,13 @@
register "PcieClkSrcClkReq[2]" = "2"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
- device pci 1c.7 on # PCI Express Port 8
+ device ref pcie_rp8 on
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
end
- device pci 1d.0 on # PCI Express Port 9 -- x4 M.2/M 2280 (NVMe)
+ device ref pcie_rp9 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[8]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
@@ -175,7 +175,7 @@
register "PcieClkSrcClkReq[0]" = "0"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
+ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
@@ -183,7 +183,7 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1f.0 on # LPC Bridge
+ device ref lpc_espi on
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
register "gen1_dec" = "0x00040069"
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
index cab254a..f9baef2 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
@@ -20,7 +20,7 @@
# Actual device tree
device domain 0 on
- device pci 14.0 on # USB xHCI
+ device ref xhci on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
@@ -123,12 +123,12 @@
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
end
- device pci 17.0 on # SATA
+ device ref sata on
register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1"
end
- device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN)
+ device ref pcie_rp8 on # x1 M.2/E 2230 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
@@ -136,13 +136,13 @@
register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
- device pci 1d.1 on # PCI Express Port 10
+ device ref pcie_rp10 on
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[9]" = "1"
register "PcieClkSrcUsage[3]" = "9"
register "PcieClkSrcClkReq[3]" = "3"
end
- device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
+ device ref pcie_rp13 on # x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
@@ -150,7 +150,7 @@
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1f.0 on # LPC Bridge
+ device ref lpc_espi on
chip superio/ite/it8528e
device pnp 2e.1 on # UART1
io 0x60 = 0x3F8
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Gerrit-Change-Id: I87cec9026bcb621ceb7eae51f65ae35bc31d584a
Gerrit-Change-Number: 80056
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>
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Attention is currently required from: Arthur Heymans, Karthik Ramasubramanian, Krishna P Bhat D, Nick Vaccaro, Paul Menzel, Poornima Tom, Subrata Banik, Vamshi Krishna Gopal.
Vamshi Krishna Gopal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79415?usp=email )
Change subject: mb/intel/adlrvp: Add Realtek ALC256 audio verb table
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> wondering if the ALC256 verb table is generic? if yes, then can we check that into vendorcode ? so o […]
Good Suggestion Subrata, Yes ALC256 verb table is generic. Verb table can be design agnostic.
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Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80055?usp=email )
Change subject: mb/purism/librem_l1um_v2: Use chipset dt reference names
......................................................................
mb/purism/librem_l1um_v2: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: Id592241a1dc33559115800da10a57a5fc10867f9
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/purism/librem_l1um_v2/devicetree.cb
1 file changed, 38 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/80055/1
diff --git a/src/mainboard/purism/librem_l1um_v2/devicetree.cb b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
index 0144f22..e86b7a0 100644
--- a/src/mainboard/purism/librem_l1um_v2/devicetree.cb
+++ b/src/mainboard/purism/librem_l1um_v2/devicetree.cb
@@ -40,20 +40,20 @@
device cpu_cluster 0 on end
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 01.0 on # PCIE6 - x16 or x8
+ device ref system_agent on end
+ device ref peg0 on # x16 or x8
register "PcieClkSrcUsage[3]" = "0x40"
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "PCIE6" "SlotDataBusWidth16X"
end
- device pci 01.1 on # PCIE4 - x8
+ device ref peg1 on # x8
register "PcieClkSrcUsage[4]" = "0x41"
smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthOther" "PCIE4" "SlotDataBusWidth8X"
end
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 off end # SA Thermal Device
- device pci 08.0 on end # Gaussian Mixture
- device pci 12.0 on end # Thermal Subsystem
- device pci 14.0 on # USB xHCI
+ device ref igpu on end
+ device ref dptf off end
+ device ref gna on end
+ device ref thermal on end
+ device ref xhci on
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front left
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front right
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port A
@@ -176,20 +176,20 @@
end
end
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 14.2 on end # RAM controller
- device pci 14.3 off end
- device pci 14.5 off end # SDCard
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE Redirection
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 17.0 on
+ device ref xdci off end
+ device ref shared_sram on end
+ device ref cnvi_wifi off end
+ device ref sdxc off end
+ device ref i2c0 off end
+ device ref i2c1 off end
+ device ref i2c2 off end
+ device ref i2c3 off end
+ device ref heci1 off end
+ device ref heci2 off end
+ device ref csme_ider off end
+ device ref csme_ktr off end
+ device ref heci3 off end
+ device ref sata on
register "satapwroptimize" = "1"
register "SataPortsEnable[0]" = "1"
@@ -209,22 +209,22 @@
register "SataPortsHotPlug[5]" = "1"
register "SataPortsHotPlug[6]" = "1"
register "SataPortsHotPlug[7]" = "1"
- end # SATA
- device pci 1b.4 on # PCI Express Port 21 - PCIE5
+ end
+ device ref pcie_rp21 on
register "PcieRpSlotImplemented[20]" = "1"
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[10]" = "20"
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "PCIE5" "SlotDataBusWidth4X"
end
- device pci 1c.0 on # PCI Express Port 1 - M2_1
+ device ref pcie_rp1 on
register "PcieRpSlotImplemented[0]" = "1"
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieClkSrcUsage[1]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X"
end
- device pci 1d.0 on # PCI Express Port 9 - GbE #1
+ device ref pcie_rp9 on # GbE #1
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[14]" = "8"
@@ -237,12 +237,12 @@
smbios_dev_info 1
end
end
- device pci 1d.1 on # PCI Express Port 10 - BMC video
+ device ref pcie_rp10 on # BMC video
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "1"
register "PcieClkSrcUsage[8]" = "9"
end
- device pci 1d.2 on # PCI Express Port 11 - GbE #2
+ device ref pcie_rp11 on # GbE #2
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "PcieClkSrcUsage[11]" = "10"
@@ -250,11 +250,11 @@
smbios_dev_info 2
end
end
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device ref uart0 off end
+ device ref uart1 off end
+ device ref gspi0 off end
+ device ref gspi1 off end
+ device ref lpc_espi on
# This board has a lot of SuperIO LDNs with I/O BARs, the LPC generic
# I/O ranges must be configured manually.
register "gen1_dec" = "0x000c0ca1" # IPMI: ca0-caf
@@ -385,10 +385,10 @@
device pnp 0c31.0 on end
end
end
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # PMC
- device pci 1f.3 off end # Intel HDA
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # SPI
+ device ref p2sb off end
+ device ref pmc hidden end
+ device ref hda off end
+ device ref smbus on end
+ device ref fast_spi on end
end
end
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