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Change subject: acpi: Add SPCR table
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
> See CB:76158
But Rex, Myst, Hades all hit the hang up issue without add console=ttyS0.115200n8. Kernel are 5.15 and 6.1. Anyone have the same issue?
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Change subject: mb/google/rex/var/screebo:Fix touchsreen thd:dat test fail
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> please add I2C timing into comment. Also the delta for the timing.
Done
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Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
Patch Set 9:
(6 comments)
File src/mainboard/inventec/transformers/Kconfig:
https://review.coreboot.org/c/coreboot/+/75598/comment/ead0d39f_6b0d0d8c :
PS8, Line 24: string
> Please remove, no need to to redefine the type
@
File src/mainboard/inventec/transformers/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75598/comment/404083a0_6e8e3b91 :
PS5, Line 23: * For ArcherCity CRB, only SUART1 is used.
> This seems copy-pasted.
@Paul Menzel This part is same as the AecherCity.
File src/mainboard/inventec/transformers/romstage.c:
https://review.coreboot.org/c/coreboot/+/75598/comment/b08275f0_086e06f2 :
PS5, Line 16: void mainboard_ewl_check(void)
> What is ewl? Please add a comment to the function.
Done
https://review.coreboot.org/c/coreboot/+/75598/comment/74270879_22bc34da :
PS5, Line 102: selftest result first */
> Please align the line correctly.
Done
https://review.coreboot.org/c/coreboot/+/75598/comment/8eb263c8_89007058 :
PS5, Line 118: /* Enable - Portions of memory reference code will be skipped */
: /* when possible to increase boot speed on warm boots.*/
: /* Disable - Disables this feature. */
: /* Auto - Sets it to the MRC default setting. */
> Please use the multi-line commenting style listed in the coding style.
Done
https://review.coreboot.org/c/coreboot/+/75598/comment/ad584745_1f80c936 :
PS5, Line 142: /* Disable FSP memory train results*/
> Please add a space at the end.
Done
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Hello Angel Pons, Arthur Heymans, David Hendricks, Felix Singer, Hung-Wei Chen, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75598?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins)
Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
mb/inventec: Add Intel SPR server board Inventec Transformers
CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector
BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC
Test:
The board boots to Linux 4.19.6 with all 192 cores available.
Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET(a)inventec.com>
---
A configs/builder/config.transformers
A src/mainboard/inventec/Kconfig
A src/mainboard/inventec/Kconfig.name
A src/mainboard/inventec/transformers/Kconfig
A src/mainboard/inventec/transformers/Kconfig.name
A src/mainboard/inventec/transformers/Makefile.inc
A src/mainboard/inventec/transformers/acpi/platform.asl
A src/mainboard/inventec/transformers/board.fmd
A src/mainboard/inventec/transformers/board_info.txt
A src/mainboard/inventec/transformers/bootblock.c
A src/mainboard/inventec/transformers/devicetree.cb
A src/mainboard/inventec/transformers/dsdt.asl
A src/mainboard/inventec/transformers/include/mainboard_ras.h
A src/mainboard/inventec/transformers/include/sprsp_ac_iio.h
A src/mainboard/inventec/transformers/include/sprsp_gpio.h
A src/mainboard/inventec/transformers/ipmi.c
A src/mainboard/inventec/transformers/ipmi.h
A src/mainboard/inventec/transformers/ramstage.c
A src/mainboard/inventec/transformers/romstage.c
19 files changed, 936 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75598/9
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Change subject: soc/amd/common/block/uart: remove DRIVERS_UART_8250MEM
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa/var/joxer: Disable external fivr
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Do you want add FW config for it? Or let previous device fail at suspend?
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Change subject: soc/amd/common/block/uart: remove DRIVERS_UART_8250MEM
......................................................................
Patch Set 2: Code-Review+2
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