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Change subject: mb/google/nissa/var/joxer: Disable external fivr
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> We have verified this CL on proto MB, both eMMC and UFS can enter S0i3 successfully, thanks.
oh weird, but fine.
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Change subject: mb/google/nissa/var/joxer: Disable external fivr
......................................................................
Patch Set 1: Code-Review+2
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Hello Angel Pons, Arthur Heymans, David Hendricks, Felix Singer, Hung-Wei Chen, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75598?usp=email
to look at the new patch set (#10).
Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
mb/inventec: Add Intel SPR server board Inventec Transformers
CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector
BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC
Test:
The board boots to Linux 4.19.6 with all 192 cores available.
dmesg --level alert,crit,err,warn:
<3>usb usb1-port3: over-current condition
<3>usb usb1-port5: over-current condition
<3>usb usb1-port6: over-current condition
<3>usb usb1-port7: over-current condition
<3>usb usb1-port8: over-current condition
<4>nvme nvme0: missing or invalid SUBNQN field.
<4>pnp 00:01: disabling [io 0x0010-0x001f] because it overlaps
0000:00:18.0 BAR 4 [io 0x0000-0x001f]
Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET(a)inventec.com>
---
A configs/builder/config.transformers
A src/mainboard/inventec/Kconfig
A src/mainboard/inventec/Kconfig.name
A src/mainboard/inventec/transformers/Kconfig
A src/mainboard/inventec/transformers/Kconfig.name
A src/mainboard/inventec/transformers/Makefile.inc
A src/mainboard/inventec/transformers/acpi/platform.asl
A src/mainboard/inventec/transformers/board.fmd
A src/mainboard/inventec/transformers/board_info.txt
A src/mainboard/inventec/transformers/bootblock.c
A src/mainboard/inventec/transformers/devicetree.cb
A src/mainboard/inventec/transformers/dsdt.asl
A src/mainboard/inventec/transformers/include/mainboard_ras.h
A src/mainboard/inventec/transformers/include/sprsp_ac_iio.h
A src/mainboard/inventec/transformers/include/sprsp_gpio.h
A src/mainboard/inventec/transformers/ipmi.c
A src/mainboard/inventec/transformers/ipmi.h
A src/mainboard/inventec/transformers/ramstage.c
A src/mainboard/inventec/transformers/romstage.c
19 files changed, 936 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75598/10
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Change subject: mb/google/nissa/var/joxer: Disable external fivr
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Do you want add FW config for it? Or let previous device fail at suspend?
We have verified this CL on proto MB, both eMMC and UFS can enter S0i3 successfully, thanks.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76158?usp=email )
Change subject: acpi: Set checksum for SPCR table
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
The zeroes presented in generated SPCR possibly come from a later ACPI spec than what fwts is aware of. Update FWTS ?
+ lava-test-case fwts-spcr --shell fwts spcr -q -r stdout --log-filter=SKP,PAS,FAL,ABT,INO --log-level high
<LAVA_SIGNAL_STARTTC fwts-spcr>
Received signal: <STARTTC> fwts-spcr
FAILED [HIGH] SPCRInterfaceReserved: Test 1, SPCR Serial interface type 0x12 is
a reserved interface
FAILED [HIGH] SPCRUnknownInterruptType: Test 1, SPCR interrupt type field is
zero, expecting support bits to be set
FAILED [HIGH] SPCRBaudRateReserved: Test 1, SPCR Serial baud rate type 0x00 is a
reserved baud rate
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Change subject: acpi: Add SPCR table
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
9elements QA also reports
> Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16
on the change-set CB:76158, so there is more going on.
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Change subject: mb/google/nissa/var/uldren: Modify DPTF parameters
......................................................................
Patch Set 1:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76105/comment/f60611b7_9dd0a25a :
PS1, Line 7: Modify
That’s too broad. Please use a more specific verb.
https://review.coreboot.org/c/coreboot/+/76105/comment/f5e2a032_e6d086b3 :
PS1, Line 11:
Please list/enumerate the changes.
https://review.coreboot.org/c/coreboot/+/76105/comment/957bc1d2_61baee36 :
PS1, Line 14: TEST=emerge-nissa coreboot chromeos-bootimage
Don’t you need to boot it also and run some tests?
File src/mainboard/google/brya/variants/uldren/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/76105/comment/45c443b1_80605235 :
PS1, Line 109: register "tcc_offset" = "3"
Please add a comment what value that actually results in.
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Change subject: mb/google/rex/var/screebo:Fix touchsreen thd:dat test fail
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76190/comment/1932b37a_7ddb624b :
PS2, Line 7: Fix touchsreen thd:dat test fail
Maybe:
> Double data hold time to 100 ns for touchscreen test failure
https://review.coreboot.org/c/coreboot/+/76190/comment/d1c0a9f5_f29368e7 :
PS2, Line 7: mb/google/rex/var/screebo:Fix
Please add a space after the colon.
https://review.coreboot.org/c/coreboot/+/76190/comment/b79689c8_9d26cebe :
PS2, Line 9: thd:dat test fail
Please elaborate, what that test does and how that test can be run.
https://review.coreboot.org/c/coreboot/+/76190/comment/618227a2_1b59b011 :
PS2, Line 10: Change i2c[0]: data_hold_time_ns > 100ns.
Where is it documented, that this is the correct value?
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Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75598/comment/d3af8642_4d5b12c4 :
PS9, Line 23: The board boots to Linux 4.19.6 with all 192 cores available.
Pretty old version. ;-)
Would you be so kind and also paste the output of `dmesg --level alert,crit,err,warn` to the commit message?
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