Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76158?usp=email )
Change subject: acpi: Set checksum for SPCR table
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> The zeroes presented in generated SPCR possibly come from a later ACPI spec than what fwts is aware […]
Thanks for digging :) Arthur already created a PR at fwts fixing the issues https://github.com/ColinIanKing/fwts/pull/13. It's also linked in a comment on a change, but I can't find it now.
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Change subject: mb/google/rex/var/screebo: Double data hold time to 100 ns for touchscreen test failure
......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76190/comment/f113c278_5c35bf41 :
PS2, Line 7: mb/google/rex/var/screebo:Fix
> Please add a space after the colon.
Done
https://review.coreboot.org/c/coreboot/+/76190/comment/44e29db5_d747274a :
PS2, Line 7: Fix touchsreen thd:dat test fail
> Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/76190/comment/c5a9bb18_a914ea08 :
PS2, Line 9: thd:dat test fail
> Please elaborate, what that test does and how that test can be run.
Done
https://review.coreboot.org/c/coreboot/+/76190/comment/7b03db60_d376da4b :
PS2, Line 10: Change i2c[0]: data_hold_time_ns > 100ns.
> Where is it documented, that this is the correct value?
This CL has been verified and passed by EE.
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Change subject: mb/google/rex/var/screebo: Double data hold time to 100 ns for touchscreen test failure
......................................................................
mb/google/rex/var/screebo: Double data hold time to 100 ns for touchscreen test failure
Change i2c[0] parameter to met touchscreen timing.
Thd:dat > 100ns.
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae
Signed-off-by: Zhongtian Wu <wuzhongtian(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/76190/3
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Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76105?usp=email )
Change subject: mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76105/comment/ce54d729_539e131e :
PS1, Line 7: Modify
> That’s too broad. Please use a more specific verb.
Done
https://review.coreboot.org/c/coreboot/+/76105/comment/a45e6e3c_ebe44f82 :
PS1, Line 11:
> Please list/enumerate the changes.
Done
https://review.coreboot.org/c/coreboot/+/76105/comment/46acc222_0bf2ee86 :
PS1, Line 14: TEST=emerge-nissa coreboot chromeos-bootimage
> Don’t you need to boot it also and run some tests?
Done
File src/mainboard/google/brya/variants/uldren/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/76105/comment/1869dc79_9be9945d :
PS1, Line 109: register "tcc_offset" = "3"
> Please add a comment what value that actually results in.
Done
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Change subject: mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset
......................................................................
mb/google/nissa/var/uldren: Update DPTF parameters and tcc_offset
Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to
modify DPTF parameters and tcc_offset.
- Set tcc_offset to 3.
- Update Critical Policy trip point.
- Update Power Limits PL1 minimum step size to control limits (in mW).
BUG=b:282598257
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---
M src/mainboard/google/brya/variants/uldren/overridetree.cb
1 file changed, 7 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/76105/2
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