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Change subject: mb/{google,intel}: Choose correct SoC type between MTL-U/P and MTL-S
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
......................................................................
soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
This patch ensures to update the FSP-M UPDs related to PCIe RP mask
properly as per the SoC type.
For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P wherelese
PCIe RPs are from PCH die in case of MTL-S.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: Ice81553274682476bb4c927061b1196dc142836d
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/romstage/fsp_params.c
1 file changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/75608/1
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 0173060..bdc4f7a 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -73,9 +73,18 @@
}
/* PCIE ports */
- m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table());
- pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp,
- get_max_pcie_port());
+ if (CONFIG(SOC_INTEL_METEORLAKE_U_P)) {
+ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table());
+ m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */
+ pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp,
+ get_max_pcie_port());
+ } else {
+ /*
+ * FIXME: Implement PCIe RP mask for `PchPcieRpEnableMask` and
+ * perform pcie_rp_init().
+ */
+ m_cfg->PcieRpEnableMask = 0; /* Don't care about SOC/IOE PCIE RP Mask */
+ }
}
static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,
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Change subject: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
......................................................................
soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
This patch introduces the different SoC flavors of Intel Meteor Lake,
for example: MTL-U, MTL-P and MTL-S.
MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die.
The ask for mainboard is to specify the correct SoC type rather than
selecting the MTL SoC by default.
This change is necessary to support the different SoC flavors of Intel
Meteor Lake.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/75606/1
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index db347af..05eb2c9 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -1,7 +1,23 @@
config SOC_INTEL_METEORLAKE
bool
help
- Intel Meteorlake support
+ Intel Meteorlake support. Mainboards should specify the SoC
+ type using the `SOC_INTEL_METEORLAKE_*` options instead
+ of selecting this option directly.
+
+config SOC_INTEL_METEORLAKE_U_P
+ bool
+ select SOC_INTEL_METEORLAKE
+ help
+ Choose this option if your mainboard has a MTL-U (15W) or MTL-P (28W) SoC.
+ Important to note that MTL-U/P SoC combines Compute, GFX, SoC and IOE die.
+
+config SOC_INTEL_METEORLAKE_S
+ bool
+ select SOC_INTEL_METEORLAKE
+ help
+ Choose this option if your mainboard has a MTL-S (45W) SoC.
+ Important to note that MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die.
if SOC_INTEL_METEORLAKE
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The following approvals got outdated and were removed:
Code-Review+1 by Tarun Tuli, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
......................................................................
soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
Hook the PchHdaSdiEnable upd so that mainboard can change the
settings via devicetree. PchHdaSdiEnable Upd enable HDA SDI lanes.
BUG=b:273962021
TEST=Verified the settings on google/rex using debug FSP logs.
Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75529/4
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Change subject: soc/amd/common/data_fabric/domain: provide scan_bus and read_resources
......................................................................
Patch Set 14: Code-Review+1
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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75280?usp=email )
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Change subject: Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Need time to test on my board first before revert this.
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