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Change subject: soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75606/comment/9d6ec70f_9558dd9c :
PS1, Line 10: for example: MTL-U, MTL-P and MTL-S.
Could you list all?
https://review.coreboot.org/c/coreboot/+/75606/comment/4e557249_273f37a2 :
PS1, Line 13: ask
task
File src/soc/intel/meteorlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/75606/comment/e69996f7_41eda427 :
PS1, Line 20: Important to note that MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die.
Maybe:
> Note, MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die.
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Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block
......................................................................
Patch Set 17: Code-Review+1
(6 comments)
File src/soc/intel/common/block/oc_wdt/Kconfig:
https://review.coreboot.org/c/coreboot/+/68944/comment/232952da_03a0bcb6 :
PS16, Line 7: config SOC_INTEL_COMMON_OC_WDT_ENABLE
> The main reason the OC WDT has an enable switch is because we don't know what payload an OS the boar […]
I agree with Michał. It's also common to have one Kconfig to express SoC support
and one for the user's choice.
https://review.coreboot.org/c/coreboot/+/68944/comment/b61cbd1c_f094751a :
PS16, Line 21: default 90
> True, DDR5 takes much longer to train. […]
LGTM. Maximilian, what do you think?
File src/soc/intel/common/block/oc_wdt/Kconfig:
https://review.coreboot.org/c/coreboot/+/68944/comment/f27abfef_a26f54b2 :
PS17, Line 41:
Just wondering, should there be an option to disable the WDT at the end of
coreboot when everything seems fine? Then one could use it for the memory
training, but doesn't need special OS support or the periodic SMI slowing
things down.
File src/soc/intel/common/block/oc_wdt/oc_wdt.c:
https://review.coreboot.org/c/coreboot/+/68944/comment/d323d8a7_15c5b0e5 :
PS17, Line 36: PCH_OC_WDT_CTL_FORCE_ALL
I don't fully understand the description of this bit. Do you have
any details about what it does? experienced a difference with it
being set/unset?
https://review.coreboot.org/c/coreboot/+/68944/comment/d1b8ce22_8683b126 :
PS17, Line 62: unsigned int oc_wdt_get_current_timeout(void)
: {
: return (inl(PCH_OC_WDT_CTL) & PCH_OC_WDT_CTL_TOV_MASK) + 1;
: }
Was this tested? I couldn't find a hint in the register description that
this would reflect the current value.
File src/soc/intel/common/block/smm/smm.c:
https://review.coreboot.org/c/coreboot/+/68944/comment/bc168ebe_0ec651e8 :
PS15, Line 45: Also we do not allow timeouts lower than 60s
> Added it to the comment.
Acknowledged
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Change subject: soc/intel/apollolake/include/soc/pmc.h: Add file
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/69900/comment/e06856f8_38699133 :
PS5, Line 10: pm.h
> I was thinking about it, but when I saw what other SoCs include in the pm.h and pmc. […]
Ping, Angel
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Change subject: mb/google/kukui: change Juniper/Willow RAM table offset to 0x30
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75563/comment/6b319382_c850e790 :
PS3, Line 7: change
Change
https://review.coreboot.org/c/coreboot/+/75563/comment/9c404850_7a55cad2 :
PS3, Line 9: leverage same RAMID
reuse the RAM ID in
https://review.coreboot.org/c/coreboot/+/75563/comment/30e4e9cc_3bfe84e2 :
PS3, Line 9: memory source
DRAM module
https://review.coreboot.org/c/coreboot/+/75563/comment/69e35cda_fb6f85dd :
PS3, Line 10: default as
offset to
https://review.coreboot.org/c/coreboot/+/75563/comment/5b9c193c_1238daaf :
PS3, Line 11: for further memory 2nd source.
for introducing more DRAM modules.
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Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/rex/variants/rex0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/75525/comment/8962ea0d_51b34c4c :
PS4, Line 37: ish_enable_pads
GPIOs, mentioned in b/283477280#comment3, are still missing.
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Change subject: mb/google/jacuzzi/: Add new variant Bellis
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> What is the state of this change-set? Was *bellis* ever created?
The project cancelled. Please abandon this patch.
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