coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/myst: Correct CROS_WP_GPIO to active high
by Jon Murphy (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Eric Lai, Karthik Ramasubramanian, Tim Van Patten. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75628?usp=email ) Change subject: mb/google/myst: Correct CROS_WP_GPIO to active high ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25 Gerrit-Change-Number: 75628 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 06 Jun 2023 03:32:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Bao Zheng (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Hello Arthur Heymans, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75405?usp=email to look at the new patch set (#6). Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... soc/amd/smm: Check the SMM TSEG size As per AMD64 Architecture Progrmamer's Manual, section 10.2.5 SMRAM Protected Areas: The TSeg range must be aligned to a 128 Kbyte boundary and the minimum TSeg size is 128 Kbytes. Plus, the SMM TSEG size should be less than SMM reserved size. I can only find the some scattered evidence proving it should be power of 2, like ${src}/cpu/intel/model_2065x/model_2065x.h Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/smm.h 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/75405/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 6 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/myst: Enable FPMCU on UART
by Eric Lai (Code Review) 06 Jun '23

06 Jun '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75629?usp=email ) Change subject: mb/google/myst: Enable FPMCU on UART ...................................................................... mb/google/myst: Enable FPMCU on UART Add FPMCU into device tree. Also set RST to low per HW request. BUG=b:285799911 TEST=check ectool --name=cros_fp version. RO version: bloonchipper_v2.0.5938-197506c1 RO cros fwid: CROS_FWID_MISSING RW version: bloonchipper_v2.0.14348-e5fb0b9 RW cros fwid: bloonchipper_14931.0.0 Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc --- M src/mainboard/google/myst/Kconfig M src/mainboard/google/myst/variants/baseboard/gpio.c M src/mainboard/google/myst/variants/myst/overridetree.cb 3 files changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75629/1 diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index dbce4d8..a35596c 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -13,6 +13,7 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_WIFI_GENERIC + select DRIVERS_UART_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index 9b0de5a..7979763 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -68,7 +68,7 @@ /* WWAN_AUX_RST_L */ PAD_GPO(GPIO_39, HIGH), /* SOC_FP_RST_L */ - PAD_GPO(GPIO_40, HIGH), + PAD_GPO(GPIO_40, LOW), /* GPIO_41 - GPIO_66: Not available */ /* GPIO_67 (Unused) */ PAD_NC(GPIO_67), diff --git a/src/mainboard/google/myst/variants/myst/overridetree.cb b/src/mainboard/google/myst/variants/myst/overridetree.cb index d701dea..d230e50 100644 --- a/src/mainboard/google/myst/variants/myst/overridetree.cb +++ b/src/mainboard/google/myst/variants/myst/overridetree.cb @@ -93,4 +93,22 @@ device i2c 2a on end end end # I2C3 + device ref uart_1 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_18)" + register "wake" = "GEVENT_14" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_40)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_4)" + register "enable_delay_ms" = "3" + device generic 0 alias fpmcu on + probe FP UART + end + end + end end # chip soc/amd/phoenix -- To view, visit https://review.coreboot.org/c/coreboot/+/75629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09819037b80e55edeb56faef9e27fe0753748efc Gerrit-Change-Number: 75629 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/myst: Correct CROS_WP_GPIO to active high
by Eric Lai (Code Review) 06 Jun '23

06 Jun '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75628?usp=email ) Change subject: mb/google/myst: Correct CROS_WP_GPIO to active high ...................................................................... mb/google/myst: Correct CROS_WP_GPIO to active high HW has invert the signal, set it to active high. BUG=b:285964562 TEST=check crossystem wpsw_cur change as expected. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25 --- M src/mainboard/google/myst/chromeos.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/75628/1 diff --git a/src/mainboard/google/myst/chromeos.c b/src/mainboard/google/myst/chromeos.c index e488e81..83ff403 100644 --- a/src/mainboard/google/myst/chromeos.c +++ b/src/mainboard/google/myst/chromeos.c @@ -8,6 +8,6 @@ static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), - CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, GPIO_DEVICE_NAME), }; DECLARE_CROS_GPIOS(cros_gpios); -- To view, visit https://review.coreboot.org/c/coreboot/+/75628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25 Gerrit-Change-Number: 75628 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Bao Zheng (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75405/comment/dfcb55f6_489bc848 : PS3, Line 10: The SMM TSEG size should be less than SMM reserved size, bigger than : 8M, and power of 2. > Done. […] I can not find the solid proof that it should be power of 2. I checked the AGESA and platform code. They do use the value of power of 2 but don't say why. -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 02:49:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Bao Zheng (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email ) Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75405/comment/a93a2c8e_c0e4bc04 : PS4, Line 11: > As the datasheet section was already mentioned, please document the source: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jun 2023 02:09:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/smm: Check the SMM TSEG size
by Bao Zheng (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, Zheng Bao. Hello Arthur Heymans, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75405?usp=email to look at the new patch set (#5). Change subject: soc/amd/smm: Check the SMM TSEG size ...................................................................... soc/amd/smm: Check the SMM TSEG size As per AMD64 Architecture Progrmamer's Manual, section 10.2.5 SMRAM Protected Areas: The SMM TSEG size should be less than SMM reserved size, bigger than 128K, and power of 2. Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/smm.h 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/75405/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: [WIP] soc/intel/meteorlake: Exclude CBMEM from TME and gen new key on...
by Pratikkumar V Prajapati (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75627?usp=email ) Change subject: [WIP] soc/intel/meteorlake: Exclude CBMEM from TME and gen new key on each reboot ...................................................................... [WIP] soc/intel/meteorlake: Exclude CBMEM from TME and gen new key on each reboot WIP DO NOT MERGE. For test only. Bug=b:276120526 TEST=TBD Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/75627/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 3f7f883..effc265 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -54,6 +54,8 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 + select INTEL_TME_EXCLUDE_CBMEM + select INTEL_TME_GEN_NEW_KEY_EACH_REBOOT select IOAPIC select MICROCODE_BLOB_UNDISCLOSED select MP_SERVICES_PPI_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3161ab99b83fb7765646be31978942f271ba1f9e Gerrit-Change-Number: 75627 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: [WIP] soc/intel/meteorlake: Set UPDs for TME exclusion range and new ...
by Pratikkumar V Prajapati (Code Review) 06 Jun '23

06 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75626?usp=email ) Change subject: [WIP] soc/intel/meteorlake: Set UPDs for TME exclusion range and new key on each reboot ...................................................................... [WIP] soc/intel/meteorlake: Set UPDs for TME exclusion range and new key on each reboot WIP DO NOT MERGE. For test only. Bug=b:276120526 TEST=TBD Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/75626/1 diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index bdc4f7a..a1d8825 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -8,6 +8,7 @@ #include <drivers/wifi/generic/wifi.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> +#include <intelbasecode/ramtop.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> #include <option.h> @@ -179,6 +180,18 @@ /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; m_cfg->TmeEnable = CONFIG(INTEL_TME) && is_tme_supported(); + + if (m_cfg->TmeEnable) { + m_cfg->GenerateNewTmeKey = CONFIG(INTEL_TME_GEN_NEW_KEY_EACH_REBOOT); + if (CONFIG(INTEL_TME_EXCLUDE_CBMEM)) { + m_cfg->TmeExcludeBase = (get_ramtop_addr() - 16*MiB); + m_cfg->TmeExcludeSize = 16*MiB; + } + } + printk(BIOS_DEBUG, "TmeEnable = %d\n", m_cfg->TmeEnable); + printk(BIOS_DEBUG, "Tme GenerateNewTmeKey = %d\n", m_cfg->GenerateNewTmeKey); + printk(BIOS_DEBUG, "TmeExcludeBase = 0x%llx\n", m_cfg->TmeExcludeBase); + printk(BIOS_DEBUG, "TmeExcludeSize = 0x%llx\n", m_cfg->TmeExcludeSize); } static void fill_fspm_uart_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/75626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8d33f470977ce8db2fd137bab9c63e325b4a32d Gerrit-Change-Number: 75626 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Pratikkumar V Prajapati (Code Review) 06 Jun '23

06 Jun '23

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75625?usp=email ) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... soc/intel/common: Introduce configs for TME exclusion range and new key generation Add INTEL_TME_EXCLUDE_CBMEM config option to allow cbmem to get excluded from being encrypted by Intel TME Add INTEL_TME_GEN_NEW_KEY_EACH_REBOOT config option to program TME to generate a new key for each reboot. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75625/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8b30dcf..941b393 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -142,6 +142,20 @@ it would get enabled. If CPU supports MKTME, this same config option enables MKTME. +config INTEL_TME_EXCLUDE_CBMEM + bool "Exclude CBMEM from TME encryption" + depends on INTEL_TME + default n + help + Exclude CBMEM from being encrypted by Intel TME. + +config INTEL_TME_GEN_NEW_KEY_EACH_REBOOT + bool "Generate new TME key on each reboot" + depends on INTEL_TME + default n + help + Program Intel TME to generate a new key on each reboot. + config CPU_XTAL_HZ int help -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newchange

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