coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: TEST: Add OEM variables functionality
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/54279?usp=email ) Change subject: TEST: Add OEM variables functionality ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/54279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fe600b2be66a33726c0de79b9a67bdcc9ad8235 Gerrit-Change-Number: 54279 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: HACK: Enable PCIe refclk 100M usb
by Qizhong Cheng (Code Review) 10 Jun '23

10 Jun '23

Qizhong Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48725 ) Change subject: HACK: Enable PCIe refclk 100M usb ...................................................................... HACK: Enable PCIe refclk 100M usb Don't pull into TOT. Thanks. A temporary patch for PCIe compliance test. Set GPIO65 pinmux for PCIe function which is clkreq#. Signed-off-by: mtk20626 <qizhong.cheng(a)mediatek.com> Change-Id: I978a2fa86fda8287436846e22ee3d8e2ced672ef --- M src/soc/mediatek/mt8192/usb.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/48725/1 diff --git a/src/soc/mediatek/mt8192/usb.c b/src/soc/mediatek/mt8192/usb.c index 44f2f15..08153d6 100644 --- a/src/soc/mediatek/mt8192/usb.c +++ b/src/soc/mediatek/mt8192/usb.c @@ -12,4 +12,5 @@ /* power on SSUSB SRAM FIFO */ setbits32(REG_SPM_POWERON_CONFIG_EN, 0xB160001); clrbits32(REG_SPM_SSPM_PWR_CON, 0x000001FF); + setbits32(REG_SPM_POWERON_CONFIG_EN + 0x380, 0x33); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I978a2fa86fda8287436846e22ee3d8e2ced672ef Gerrit-Change-Number: 48725 Gerrit-PatchSet: 1 Gerrit-Owner: Qizhong Cheng <qizhong.cheng(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]soc/intel/xeon_sp: Allow experimental long mode support
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48502 ) Change subject: [WIP]soc/intel/xeon_sp: Allow experimental long mode support ...................................................................... [WIP]soc/intel/xeon_sp: Allow experimental long mode support The acpi_create_rmrr code needs to be cleaned up. Change-Id: I96817f69cdcaa1ea040bc328c50f5ab23c637cb2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/nb_acpi.c 3 files changed, 20 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/48502/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..8d9e469 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -25,7 +25,8 @@ config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_ALL_STAGES_X86_32 + select ARCH_ALL_STAGES_X86_32 if !EXP_ARCH_X86_64 + select ARCH_ALL_STAGES_X86_64 if EXP_ARCH_X86_64 select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 4fe8b20..807083f 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -219,9 +219,9 @@ // apm_control(APM_CNT_GNVS_UPDATE); /* Add it to DSDT. */ - printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); + printk(BIOS_SPEW, "%s injecting NVSA with 0x%lx\n", __FILE__, (uintptr_t)gnvs); acpigen_write_scope("\\"); - acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_write_name_dword("NVSA", (uint32_t)(uintptr_t)gnvs); acpigen_pop_len(); } } diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 19c3921..f586d9b 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -292,11 +292,11 @@ for (int stack = 0; stack <= PSTACK2; ++stack) { uint32_t bus = iio_resource.StackRes[stack].BusBase; - uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + uintptr_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; if (!vtd_base) continue; uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%lx, " "vtd_mmio_cap: 0x%llx\n", __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); @@ -322,24 +322,24 @@ static unsigned long acpi_create_rmrr(unsigned long current) { - uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); +// uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); - uint32_t *ptr; + /* uint32_t *ptr; */ - // reserve memory - ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); - if (!ptr) { - ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); - assert(ptr != NULL); - memset(ptr, 0, size); - } + /* // reserve memory */ + /* ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); */ + /* if (!ptr) { */ + /* ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); */ + /* assert(ptr != NULL); */ + /* memset(ptr, 0, size); */ + /* } */ unsigned long tmp = current; - printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " - "End Address (limit): 0x%x\n", - 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); - current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, - (uint32_t) ((uint32_t) ptr + size - 1)); + /* printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " */ + /* "End Address (limit): 0x%x\n", */ + /* 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); */ + /* current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, */ + /* (uint32_t) ((uint32_t) ptr + size - 1)); */ printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/48502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96817f69cdcaa1ea040bc328c50f5ab23c637cb2 Gerrit-Change-Number: 48502 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32350?usp=email ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/32350?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan L Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41852 ) Change subject: sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler ...................................................................... sb/intel/bd82x6x/smihandler: Fix xHCI sleep handler The xHCI S3/S4 quirk is only needed on PPT Revision A0. Fix always false condition by adding the missing read32 function call. Untested. Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/smihandler.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/41852/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index cddb4cf..fbc7b81 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -100,6 +100,9 @@ switch (slp_typ) { case ACPI_S3: case ACPI_S4: + if (!pch_silicon_supported(PCH_TYPE_PPT, PCH_STEP_A0)) + break; + reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 &= ~0x03UL; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); @@ -112,14 +115,13 @@ PCI_BASE_ADDRESS_0) & ~0xFUL; if (!smm_validate_pointer((void *)(uintptr_t)xhci_bar)) { - /* FIXME: This looks broken */ - if ((xhci_bar + 0x4C0) & 1) + if (read32(xhci_bar + 0x4C0) & 1) pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4D0) & 1) + if (read32(xhci_bar + 0x4D0) & 1) pch_iobp_update(0xEC000182, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4E0) & 1) + if (read32(xhci_bar + 0x4E0) & 1) pch_iobp_update(0xEC000282, ~0UL, (3 << 2)); - if ((xhci_bar + 0x4F0) & 1) + if (read32(xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); } reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); -- To view, visit https://review.coreboot.org/c/coreboot/+/41852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc658aa9fe11c8ee93290e3d3ef66e73476f3c57 Gerrit-Change-Number: 41852 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/clevo/l140cu: Add vboot support
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46602?usp=email ) Change subject: mb/clevo/l140cu: Add vboot support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/46602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb5e93eb55ece5b0e0d91b1a374d33e259c65cac Gerrit-Change-Number: 46602 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/common: Use ACPIMMIO_BASE() in ASL
by Kyösti Mälkki (Code Review) 10 Jun '23

10 Jun '23

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42944 ) Change subject: soc/amd/common: Use ACPIMMIO_BASE() in ASL ...................................................................... soc/amd/common: Use ACPIMMIO_BASE() in ASL Change-Id: Iff6bdbe5a12f1a47c7ce348a628e0b67aac37c7c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/soc/amd/common/acpi/gpio_bank_lib.asl M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/picasso/acpi/sb_fch.asl M src/soc/amd/stoneyridge/acpi/sb_fch.asl 5 files changed, 7 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/42944/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 837678a..f61f6a0 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -22,7 +22,7 @@ Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Return (RBUF) diff --git a/src/soc/amd/common/acpi/gpio_bank_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl index f73340c..b60fba91 100644 --- a/src/soc/amd/common/acpi/gpio_bank_lib.asl +++ b/src/soc/amd/common/acpi/gpio_bank_lib.asl @@ -6,7 +6,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) + Return (Add(Multiply(Arg0, 4), ACPIMMIO_BASE(GPIO0))) } /* Read pin control dword */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index e5caefc..e8f4625 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -94,12 +94,6 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#ifdef __ACPI__ -/* ASL MemoryFixed32() fails if these are additions. */ -#define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#endif - #define ACPIMMIO_SM_PCI_BANK 0x0000 #define ACPIMMIO_GPIO_100_BANK 0x0100 #define ACPIMMIO_SMI_BANK 0x0200 diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 007df8d..d283402 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -34,7 +34,7 @@ ActiveLow, Exclusive, , , IRQR) { 0 } - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) } CreateDWordField (Local0, IRQR._INT, IRQN) If (PMOD) { @@ -44,7 +44,7 @@ } If (IRQN == 0x1f) { Return (ResourceTemplate() { - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) }) } Else { Return (Local0) @@ -396,7 +396,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index c999b67..9adb82a 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -30,7 +30,7 @@ { Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) { 7 } - Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x300) + Memory32Fixed (ReadWrite, ACPIMMIO_BASE(GPIO0), 0x300) }) Method (_STA, 0x0, NotSerialized) @@ -132,7 +132,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_BASE(MISC), 0x100) }) Method (_STA, 0x0, NotSerialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff6bdbe5a12f1a47c7ce348a628e0b67aac37c7c Gerrit-Change-Number: 42944 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Support FSP-T in long mode
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48501 ) Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode ...................................................................... drivers/intel/fsp2_0: Support FSP-T in long mode TESTED on ocp/deltalake Change-Id: I6ce779f9d1b8733e8ca2db5e0f5e1058242e03f5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48501/1 diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index c3bfbba..b46381b 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -6,6 +6,7 @@ #include <fsp/util.h> #include <cbfs.h> #include <types.h> +#include <mode_switch.h> void fsp_temp_ram_exit(void) { @@ -26,9 +27,12 @@ if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) die("Invalid FSPM header!\n"); - temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + temp_ram_exit = (void *)(uintptr_t)(hdr.image_base + hdr.temp_ram_exit_entry); printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit); - status = temp_ram_exit(NULL); + if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) + status = protected_mode_call_1arg(temp_ram_exit, (uintptr_t)NULL); + else + status = temp_ram_exit(NULL); if (status != FSP_SUCCESS) { printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status); diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 04dc533..bb86d7b 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -12,6 +12,8 @@ .extern temp_ram_init_params +.code32 + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -94,10 +96,18 @@ pop %ecx movl %ecx, temp_memory_start +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movl %ebp, %edi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi +#else /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ push %ebp movd %mm1, %eax push %eax +#endif /* We can call into C functions now */ call bootblock_c_entry -- To view, visit https://review.coreboot.org/c/coreboot/+/48501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ce779f9d1b8733e8ca2db5e0f5e1058242e03f5 Gerrit-Change-Number: 48501 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/acer/aspire_vn7_572g: Optimus support
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40628?usp=email ) Change subject: mb/acer/aspire_vn7_572g: Optimus support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/40628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac971137ff6805628eb219adedee0c55fb8caef9 Gerrit-Change-Number: 40628 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: [WIP]device/Kconfig: Introduce separate graphics menu for Aspeed
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49218 ) Change subject: [WIP]device/Kconfig: Introduce separate graphics menu for Aspeed ...................................................................... [WIP]device/Kconfig: Introduce separate graphics menu for Aspeed Allows to select which graphics initialisation to do for Aspeed graphics. Change-Id: I63e58dfacd6cd0b8fab188e27d34ade9b1344a48 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/Kconfig A src/device/graphics/Kconfig A src/device/graphics/aspeed/Kconfig M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/Kconfig 5 files changed, 69 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/49218/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index a176f0a..ca1b4c77 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -46,13 +46,6 @@ Selected by mainboards / drivers that provide native graphics init for Intel GPUs within coreboot. -config MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT - def_bool n - select MAINBOARD_HAS_NATIVE_VGA_INIT - help - Selected by mainboards / drivers that provide native graphics - init for Aspeed GPUs within coreboot. - config MAINBOARD_HAS_NATIVE_RK3288_VGA_INIT def_bool n select MAINBOARD_HAS_NATIVE_VGA_INIT @@ -73,6 +66,8 @@ Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays. +source "src/device/graphics/Kconfig" + choice prompt "Graphics initialization" default NO_GFX_INIT if VGA_BIOS && PAYLOAD_SEABIOS diff --git a/src/device/graphics/Kconfig b/src/device/graphics/Kconfig new file mode 100644 index 0000000..f45bf30 --- /dev/null +++ b/src/device/graphics/Kconfig @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +source "src/device/graphics/aspeed/Kconfig" diff --git a/src/device/graphics/aspeed/Kconfig b/src/device/graphics/aspeed/Kconfig new file mode 100644 index 0000000..1f26629 --- /dev/null +++ b/src/device/graphics/aspeed/Kconfig @@ -0,0 +1,46 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT + def_bool n + select MAINBOARD_HAS_NATIVE_VGA_INIT + help + Selected by mainboards / drivers that provide native graphics + init for Aspeed GPUs within coreboot. + +config MAINBOARD_FORCE_NATIVE_ASPEED_VGA_INIT + def_bool n + depends on MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT + help + Selected by mainboards / chipsets whose graphics driver can't or + shouldn't be disabled. + +choice + prompt "Aspeed graphics initialization" + default DO_NATIVE_ASPEED_VGA_INIT if MAINBOARD_FORCE_NATIVE_ASPEED_VGA_INIT + default NO_ASPEED_VGA_INIT if VGA_BIOS && PAYLOAD_SEABIOS + default VGA_ROM_RUN_ASPEED_VGA_INIT if VGA_BIOS + default DO_NATIVE_ASPEED_VGA_INIT + +config DO_NATIVE_ASPEED_VGA_INIT + bool "Native" + depends on MAINBOARD_HAS_NATIVE_ASPEED_VGA_INIT + help + Selected by mainboards / drivers that do native graphics + init for Aspeed GPUs within coreboot. + +config VGA_ROM_RUN_ASPEED_VGA_INIT + bool "Legacy VGA Option ROM" + depends on !MAINBOARD_FORCE_NATIVE_ASPEED_VGA_INIT + depends on VGA_ROM_RUN + help + FIXME: This won't work unless VGA_ROM_RUN is selected as well + Selected by mainboards / drivers that do include a Aspeed VBIOS in + the CBFS for Aspeed GPUs within coreboot. + +config NO_ASPEED_VGA_INIT + bool "None" + depends on !MAINBOARD_FORCE_NATIVE_ASPEED_VGA_INIT + help + Select this to not perform any graphics initialization in + coreboot on the Aspeed GPU. +endchoice diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 5cb7198..17d5439 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -36,18 +36,24 @@ outb(0xa6, 0x3d4); outb(0x2f, 0x3d5); outb(0xa7, 0x3d4); outb(0x3f, 0x3d5); - if (CONFIG(VGA_TEXT_FRAMEBUFFER)) { - /* Initialize standard VGA text mode */ - vga_io_init(); + if (CONFIG(VGA_ROM_RUN_ASPEED_VGA_INIT)) { + pci_dev_init(dev); + } else if (CONFIG(DO_NATIVE_ASPEED_VGA_INIT)) { + if (CONFIG(VGA_TEXT_FRAMEBUFFER)) { + /* Initialize standard VGA text mode */ + vga_io_init(); - vga_textmode_init(); - printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); + vga_textmode_init(); + printk(BIOS_INFO, "ASpeed VGA text mode initialized\n"); - /* if we don't have console, at least print something... */ - vga_line_write(0, "ASpeed VGA text mode initialized"); - } else if (CONFIG(GENERIC_LINEAR_FRAMEBUFFER)) { - ast_driver_framebuffer_init(&drm_dev, 0); - printk(BIOS_INFO, "ASpeed high resolution framebuffer initialized\n"); + /* if we don't have console, at least print something... */ + vga_line_write(0, "ASpeed VGA text mode initialized"); + } else if (CONFIG(GENERIC_LINEAR_FRAMEBUFFER)) { + ast_driver_framebuffer_init(&drm_dev, 0); + printk(BIOS_INFO, "ASpeed high resolution framebuffer initialized\n"); + } + } else { + printk(BIOS_INFO, "ASpeed: Skipping graphics init.\n"); } } diff --git a/src/drivers/aspeed/common/Kconfig b/src/drivers/aspeed/common/Kconfig index 79c4c75..50d4a38 100644 --- a/src/drivers/aspeed/common/Kconfig +++ b/src/drivers/aspeed/common/Kconfig @@ -1,6 +1,6 @@ config DRIVERS_ASPEED_AST_COMMON bool - select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT - select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER if DO_NATIVE_ASPEED_VGA_INIT + select HAVE_VGA_TEXT_FRAMEBUFFER if DO_NATIVE_ASPEED_VGA_INIT select VGA if VGA_TEXT_FRAMEBUFFER select SOFTWARE_I2C if GENERIC_LINEAR_FRAMEBUFFER -- To view, visit https://review.coreboot.org/c/coreboot/+/49218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63e58dfacd6cd0b8fab188e27d34ade9b1344a48 Gerrit-Change-Number: 49218 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023