Change in coreboot[master]: drivers/intel/fsp2_0: Support FSP-T in long mode

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48501 )

Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
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drivers/intel/fsp2_0: Support FSP-T in long mode

TESTED on ocp/deltalake

Change-Id: I6ce779f9d1b8733e8ca2db5e0f5e1058242e03f5
Signed-off-by: Arthur Heymans 
---
M src/drivers/intel/fsp2_0/temp_ram_exit.c
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
2 files changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/48501/1

diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c
index c3bfbba..b46381b 100644
--- a/src/drivers/intel/fsp2_0/temp_ram_exit.c
+++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c
@@ -6,6 +6,7 @@
 #include <fsp/util.h>
 #include <cbfs.h>
 #include <types.h>
+#include <mode_switch.h>

void fsp_temp_ram_exit(void)
 {
@@ -26,9 +27,12 @@
    if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS)
    	die("Invalid FSPM header!\n");

-	temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry);
+	temp_ram_exit = (void *)(uintptr_t)(hdr.image_base + hdr.temp_ram_exit_entry);
    printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit);
-	status = temp_ram_exit(NULL);
+	if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32))
+		status = protected_mode_call_1arg(temp_ram_exit, (uintptr_t)NULL);
+	else
+		status = temp_ram_exit(NULL);

if (status != FSP_SUCCESS) {
    	printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status);
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
index 04dc533..bb86d7b 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
@@ -12,6 +12,8 @@

.extern	temp_ram_init_params

+.code32
+
 .global	bootblock_pre_c_entry
 bootblock_pre_c_entry:

@@ -94,10 +96,18 @@
    pop	%ecx
    movl	%ecx, temp_memory_start

+#if ENV_X86_64
+	#include <cpu/x86/64bit/entry64.inc>
+	movl	%ebp, %edi
+	shlq	$32, %rdi
+	movd	%mm1, %rsi
+	or	%rsi, %rdi
+#else
    /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */
    push	%ebp
    movd	%mm1, %eax
    push	%eax
+#endif

/* We can call into C functions now */
    call	bootblock_c_entry

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48501 )

Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/48501/1/src/soc/intel/common/block/... 
File src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S:

https://review.coreboot.org/c/coreboot/+/48501/1/src/soc/intel/common/block/... 
PS1, Line 100: 	#include <cpu/x86/64bit/entry64.inc>
stack isn't aligned to 16bytes

[S] Change in coreboot[master]: drivers/intel/fsp2_0: Support FSP-T in long mode

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48501?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-T in long mode
......................................................................

Abandoned