coreboot-gerrit June 2023

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[S] Change in vboot[main]: firmware/2lib: Add function to clear VB2_NV_DISPLAY_REQUEST
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/vboot/+/67277?usp=email ) Change subject: firmware/2lib: Add function to clear VB2_NV_DISPLAY_REQUEST ...................................................................... Abandoned Please submit to chromium.org. This is a read-only mirror. -- To view, visit https://review.coreboot.org/c/vboot/+/67277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: main Gerrit-Change-Id: Ib92f1077d227881c2c36b77aa83be4d6be7b3dda Gerrit-Change-Number: 67277 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik Vaghela <maulikvaghela(a)google.com> Gerrit-MessageType: abandon

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Change in ...vboot[master]: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR
by Rizwan Qureshi (Code Review) 10 Jun '23

10 Jun '23

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/32679 Change subject: vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR ...................................................................... vboot: Fix build error related to VB2_SHARED_DATA_VERSION_MINOR vboot fails to compile with the error "error: comparison is always false due to limited range of data type [-Werror=type-limits]" since struct_version_minor is uint16_t and can never be less than VB2_SHARED_DATA_VERSION_MINOR (0) Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 --- M firmware/2lib/2misc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/79/32679/1 diff --git a/firmware/2lib/2misc.c b/firmware/2lib/2misc.c index 95cbae3..195a0f9 100644 --- a/firmware/2lib/2misc.c +++ b/firmware/2lib/2misc.c @@ -128,7 +128,7 @@ return VB2_ERROR_SHARED_DATA_MAGIC; if (sd->struct_version_major != VB2_SHARED_DATA_VERSION_MAJOR || - sd->struct_version_minor < VB2_SHARED_DATA_VERSION_MINOR) + sd->struct_version_minor != VB2_SHARED_DATA_VERSION_MINOR) return VB2_ERROR_SHARED_DATA_VERSION; return VB2_SUCCESS; -- To view, visit https://review.coreboot.org/c/vboot/+/32679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: I0e68981fbecafe7ba40e00ee657e82c024a89325 Gerrit-Change-Number: 32679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in vboot[main]: vboot: Ignore Linux-specific definitions on macOS
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Alex James, Martin L Roth. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/vboot/+/60234?usp=email ) Change subject: vboot: Ignore Linux-specific definitions on macOS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please submit to chromium.org. This is a read-only mirror. -- To view, visit https://review.coreboot.org/c/vboot/+/60234?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: main Gerrit-Change-Id: Ie5cfd63d6cb17c16ec6a461589b4bc82cf668d73 Gerrit-Change-Number: 60234 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Alex James <theracermaster(a)gmail.com> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:39:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in vboot[main]: cgpt: Add endian definitions for macOS
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Alex James. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/vboot/+/60235?usp=email ) Change subject: cgpt: Add endian definitions for macOS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please submit to chromium.org. This is a read-only mirror. -- To view, visit https://review.coreboot.org/c/vboot/+/60235?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: main Gerrit-Change-Id: I87e98ea157870417f5eba63807eef559e180d1f8 Gerrit-Change-Number: 60235 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Alex James <theracermaster(a)gmail.com> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:39:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD
by David Wu (Code Review) 10 Jun '23

10 Jun '23

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75745?usp=email ) Change subject: mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD ...................................................................... mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/osiris/memory/Makefile.inc M src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/75745/1 diff --git a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc index eb91988..3a011cf 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc @@ -6,3 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt index 11359505..6d2a335 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ H54G56CYRBX247 1 (0001) K4U6E3S4AB-MGCL 0 (0000) K4UBE3D4AB-MGCL 1 (0001) +MT53E2G32D4NQ-046 WT:C 2 (0010) diff --git a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt index a188982..eab1b17 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C -- To view, visit https://review.coreboot.org/c/coreboot/+/75745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Gerrit-Change-Number: 75745 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[4.11_branch]: security/intel/stm: Provide MSEG too small diagnostic information
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55630?usp=email ) Change subject: security/intel/stm: Provide MSEG too small diagnostic information ...................................................................... security/intel/stm: Provide MSEG too small diagnostic information This patch provides diagnostic information during the STM setup to indicate when the MSEG is too small for what the STM requires. The error message includes the configured MSEG size and the MSEG area that the STM needs. Change-Id: I88d947e3a0495089be886f6557e4d4d7993e2508 Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55630 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/security/intel/stm/SmmStm.c 1 file changed, 60 insertions(+), 94 deletions(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 523a63f..e6f4c0a 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -39,8 +39,7 @@ #define STM_PAGE_SHIFT 12 #define STM_PAGE_MASK 0xFFF -#define STM_SIZE_TO_PAGES(a) \ - (((a) >> STM_PAGE_SHIFT) + (((a)&STM_PAGE_MASK) ? 1 : 0)) +#define STM_SIZE_TO_PAGES(a) (((a) >> STM_PAGE_SHIFT) + (((a)&STM_PAGE_MASK) ? 1 : 0)) #define STM_PAGES_TO_SIZE(a) ((a) << STM_PAGE_SHIFT) #define STM_ACCESS_DENIED 15 @@ -137,13 +136,10 @@ resource_hi = resource->mem.base + resource->mem.length; record_lo = record->mem.base; record_hi = record->mem.base + record->mem.length; - if (resource->mem.rwx_attributes - != record->mem.rwx_attributes) { - if ((resource_lo == record_lo) - && (resource_hi == record_hi)) { - record->mem.rwx_attributes = - resource->mem.rwx_attributes - | record->mem.rwx_attributes; + if (resource->mem.rwx_attributes != record->mem.rwx_attributes) { + if ((resource_lo == record_lo) && (resource_hi == record_hi)) { + record->mem.rwx_attributes = resource->mem.rwx_attributes + | record->mem.rwx_attributes; return true; } else { return false; @@ -153,39 +149,31 @@ case IO_RANGE: case TRAPPED_IO_RANGE: resource_lo = (uint64_t)resource->io.base; - resource_hi = (uint64_t)resource->io.base - + (uint64_t)resource->io.length; + resource_hi = (uint64_t)resource->io.base + (uint64_t)resource->io.length; record_lo = (uint64_t)record->io.base; - record_hi = - (uint64_t)record->io.base + (uint64_t)record->io.length; + record_hi = (uint64_t)record->io.base + (uint64_t)record->io.length; break; case PCI_CFG_RANGE: if ((resource->pci_cfg.originating_bus_number != record->pci_cfg.originating_bus_number) - || (resource->pci_cfg.last_node_index - != record->pci_cfg.last_node_index)) + || (resource->pci_cfg.last_node_index != record->pci_cfg.last_node_index)) return false; - if (memcmp(resource->pci_cfg.pci_device_path, - record->pci_cfg.pci_device_path, + if (memcmp(resource->pci_cfg.pci_device_path, record->pci_cfg.pci_device_path, sizeof(STM_PCI_DEVICE_PATH_NODE) * (resource->pci_cfg.last_node_index + 1)) != 0) { return false; } resource_lo = (uint64_t)resource->pci_cfg.base; - resource_hi = (uint64_t)resource->pci_cfg.base - + (uint64_t)resource->pci_cfg.length; + resource_hi = + (uint64_t)resource->pci_cfg.base + (uint64_t)resource->pci_cfg.length; record_lo = (uint64_t)record->pci_cfg.base; - record_hi = (uint64_t)record->pci_cfg.base - + (uint64_t)record->pci_cfg.length; - if (resource->pci_cfg.rw_attributes - != record->pci_cfg.rw_attributes) { - if ((resource_lo == record_lo) - && (resource_hi == record_hi)) { - record->pci_cfg.rw_attributes = - resource->pci_cfg.rw_attributes - | record->pci_cfg.rw_attributes; + record_hi = (uint64_t)record->pci_cfg.base + (uint64_t)record->pci_cfg.length; + if (resource->pci_cfg.rw_attributes != record->pci_cfg.rw_attributes) { + if ((resource_lo == record_lo) && (resource_hi == record_hi)) { + record->pci_cfg.rw_attributes = resource->pci_cfg.rw_attributes + | record->pci_cfg.rw_attributes; return true; } else { return false; @@ -256,8 +244,7 @@ // Go to next record if resource and record types don't match. if (resource->header.rsc_type != record->header.rsc_type) { - record = (STM_RSC *)((void *)record - + record->header.length); + record = (STM_RSC *)((void *)record + record->header.length); continue; } @@ -268,15 +255,13 @@ } // Add resource to the end of area. - memcpy(m_stm_resources_ptr + m_stm_resource_size_used - - sizeof(m_rsc_end_node), + memcpy(m_stm_resources_ptr + m_stm_resource_size_used - sizeof(m_rsc_end_node), resource, resource->header.length); - memcpy(m_stm_resources_ptr + m_stm_resource_size_used - - sizeof(m_rsc_end_node) + resource->header.length, + memcpy(m_stm_resources_ptr + m_stm_resource_size_used - sizeof(m_rsc_end_node) + + resource->header.length, &m_rsc_end_node, sizeof(m_rsc_end_node)); m_stm_resource_size_used += resource->header.length; - m_stm_resource_size_available = - m_stm_resource_total_size - m_stm_resource_size_used; + m_stm_resource_size_available = m_stm_resource_total_size - m_stm_resource_size_used; } /* @@ -303,8 +288,7 @@ if (resource->header.rsc_type == END_OF_RESOURCES) return; add_single_resource(resource); - resource = - (STM_RSC *)((void *)resource + resource->header.length); + resource = (STM_RSC *)((void *)resource + resource->header.length); } } @@ -336,11 +320,8 @@ resource = resource_list; for (index = 0; index < count; index++) { - printk(BIOS_DEBUG, "STM: %s (%u) - RscType(%x) length(0x%x)\n", - __func__, - index, - resource->header.rsc_type, - resource->header.length); + printk(BIOS_DEBUG, "STM: %s (%u) - RscType(%x) length(0x%x)\n", __func__, index, + resource->header.rsc_type, resource->header.length); // Validate resource. switch (resource->header.rsc_type) { case END_OF_RESOURCES: @@ -360,11 +341,8 @@ case MEM_RANGE: case MMIO_RANGE: - printk(BIOS_DEBUG, - "STM: %s - MEM (0x%0llx, 0x%0llx)\n", - __func__, - resource->mem.base, - resource->mem.length); + printk(BIOS_DEBUG, "STM: %s - MEM (0x%0llx, 0x%0llx)\n", __func__, + resource->mem.base, resource->mem.length); if (resource->header.length != sizeof(STM_RSC_MEM_DESC)) return false; @@ -383,34 +361,26 @@ break; case PCI_CFG_RANGE: - printk(BIOS_DEBUG, - "STM: %s - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", - __func__, - resource->pci_cfg.originating_bus_number, + printk(BIOS_DEBUG, "STM: %s - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", + __func__, resource->pci_cfg.originating_bus_number, resource->pci_cfg.last_node_index, resource->pci_cfg.pci_device_path[0].pci_device, - resource->pci_cfg.pci_device_path[0] - .pci_function); + resource->pci_cfg.pci_device_path[0].pci_function); if (resource->header.length != sizeof(STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * resource->pci_cfg.last_node_index)) return false; - for (sub_index = 0; - sub_index <= resource->pci_cfg.last_node_index; + for (sub_index = 0; sub_index <= resource->pci_cfg.last_node_index; sub_index++) { - if ((resource->pci_cfg - .pci_device_path[sub_index] - .pci_device + if ((resource->pci_cfg.pci_device_path[sub_index].pci_device > 0x1F) - || (resource->pci_cfg - .pci_device_path[sub_index] + || (resource->pci_cfg.pci_device_path[sub_index] .pci_function > 7)) return false; } - if ((resource->pci_cfg.base + resource->pci_cfg.length) - > 0x1000) + if ((resource->pci_cfg.base + resource->pci_cfg.length) > 0x1000) return false; break; @@ -420,12 +390,11 @@ break; default: - printk(BIOS_DEBUG, "STM: %s - Unknown RscType(%x)\n", - __func__, resource->header.rsc_type); + printk(BIOS_DEBUG, "STM: %s - Unknown RscType(%x)\n", __func__, + resource->header.rsc_type); return false; } - resource = - (STM_RSC *)((void *)resource + resource->header.length); + resource = (STM_RSC *)((void *)resource + resource->header.length); } return true; } @@ -462,8 +431,7 @@ for (index = 0; index < count; index++) { if (resource->header.rsc_type == END_OF_RESOURCES) break; - resource = - (STM_RSC *)((void *)resource + resource->header.length); + resource = (STM_RSC *)((void *)resource + resource->header.length); } return (uint32_t)((uint32_t)resource - (uint32_t)resource_list); } @@ -490,7 +458,7 @@ return -1; // INVALID_PARAMETER; resource_size = get_resource_size(resource_list, num_entries); - printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08x\n", (int) resource_size); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08x\n", (int)resource_size); if (resource_size == 0) return -1; // INVALID_PARAMETER; @@ -501,8 +469,7 @@ m_stm_resource_total_size = CONFIG_BIOS_RESOURCE_LIST_SIZE; memset(m_stm_resources_ptr, 0, CONFIG_BIOS_RESOURCE_LIST_SIZE); - memcpy(m_stm_resources_ptr, &m_rsc_end_node, - sizeof(m_rsc_end_node)); + memcpy(m_stm_resources_ptr, &m_rsc_end_node, sizeof(m_rsc_end_node)); m_stm_resource_size_used = sizeof(m_rsc_end_node); m_stm_resource_size_available = m_stm_resource_total_size - sizeof(m_rsc_end_node); @@ -511,7 +478,7 @@ } else { if (m_stm_resource_size_available < resource_size) { printk(BIOS_DEBUG, - "STM: ERROR - not enough space for SMM resource list\n"); + "STM: ERROR - not enough space for SMM resource list\n"); return -1; // OUT_OF_RESOURCES } } @@ -543,8 +510,7 @@ // Delete all memcpy(m_stm_resources_ptr, &m_rsc_end_node, sizeof(m_rsc_end_node)); m_stm_resource_size_used = sizeof(m_rsc_end_node); - m_stm_resource_size_available = - m_stm_resource_total_size - sizeof(m_rsc_end_node); + m_stm_resource_size_available = m_stm_resource_total_size - sizeof(m_rsc_end_node); return 0; // SUCCESS; } @@ -587,8 +553,8 @@ this_vmcs_size = msr_data64.bits.vmcs_size; stm_support = msr_data64.bits.stm_supported; - printk(BIOS_DEBUG, "STM: %s: Size %d StmSupport %d\n", __func__, - this_vmcs_size, stm_support); + printk(BIOS_DEBUG, "STM: %s: Size %d StmSupport %d\n", __func__, this_vmcs_size, + stm_support); // VMCS require 0x1000 alignment this_vmcs_size = STM_PAGES_TO_SIZE(STM_SIZE_TO_PAGES(this_vmcs_size)); @@ -623,10 +589,9 @@ pde++; pagetable_base += PTP_SIZE; - for (sub_index = 0; sub_index < SIZE_4KB / sizeof(*pte); - sub_index++) { - *pte = (((index << 9) + sub_index) << 21) | IA32_PG_PS - | IA32_PG_RW | IA32_PG_P; + for (sub_index = 0; sub_index < SIZE_4KB / sizeof(*pte); sub_index++) { + *pte = (((index << 9) + sub_index) << 21) | IA32_PG_PS | IA32_PG_RW + | IA32_PG_P; pte++; } } @@ -650,30 +615,31 @@ stm_header = (STM_HEADER *)stm_image; // Get Minimal required Mseg size - min_mseg_size = (STM_PAGES_TO_SIZE(STM_SIZE_TO_PAGES( - stm_header->sw_stm_hdr.static_image_size)) - + stm_header->sw_stm_hdr.additional_dynamic_memory_size - + (stm_header->sw_stm_hdr.per_proc_dynamic_memory_size - + get_vmcs_size() * 2) - * mp_state.cpu_count); + min_mseg_size = + (STM_PAGES_TO_SIZE(STM_SIZE_TO_PAGES(stm_header->sw_stm_hdr.static_image_size)) + + stm_header->sw_stm_hdr.additional_dynamic_memory_size + + (stm_header->sw_stm_hdr.per_proc_dynamic_memory_size + get_vmcs_size() * 2) + * mp_state.cpu_count); if (min_mseg_size < stm_imagesize) min_mseg_size = stm_imagesize; - if (stm_header->hw_stm_hdr.cr3_offset - >= stm_header->sw_stm_hdr.static_image_size) { + if (stm_header->hw_stm_hdr.cr3_offset >= stm_header->sw_stm_hdr.static_image_size) { // We will create page table, just in case that SINIT does not // create it. - if (min_mseg_size < stm_header->hw_stm_hdr.cr3_offset - + STM_PAGES_TO_SIZE(6)) { - min_mseg_size = stm_header->hw_stm_hdr.cr3_offset - + STM_PAGES_TO_SIZE(6); + if (min_mseg_size < stm_header->hw_stm_hdr.cr3_offset + STM_PAGES_TO_SIZE(6)) { + min_mseg_size = + stm_header->hw_stm_hdr.cr3_offset + STM_PAGES_TO_SIZE(6); } } // Check if it exceeds MSEG size - if (min_mseg_size > CONFIG_MSEG_SIZE) + if (min_mseg_size > CONFIG_MSEG_SIZE) { + printk(BIOS_ERR, + "STM: ERROR - Configured MSEG size 0x%x less than required MSEG size 0x%x\n", + CONFIG_MSEG_SIZE, min_mseg_size); return false; + } return true; } -- To view, visit https://review.coreboot.org/c/coreboot/+/55630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I88d947e3a0495089be886f6557e4d4d7993e2508 Gerrit-Change-Number: 55630 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[4.11_branch]: security/intel/stm: Provide MSEG too small diagnostic information
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55630?usp=email ) Change subject: security/intel/stm: Provide MSEG too small diagnostic information ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I88d947e3a0495089be886f6557e4d4d7993e2508 Gerrit-Change-Number: 55630 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:21:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: security/intel/stm/Makefile.inc: Fix typo
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55624?usp=email ) Change subject: security/intel/stm/Makefile.inc: Fix typo ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I8aa81a51380d48b172284e534ffd203f30a10286 Gerrit-Change-Number: 55624 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:21:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: security/intel/stm: Make sure stm_resource_heap is consistent
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55629?usp=email ) Change subject: security/intel/stm: Make sure stm_resource_heap is consistent ...................................................................... security/intel/stm: Make sure stm_resource_heap is consistent When a parallel SMM relocation is being done, there is a good chance that the value for stm_resource_heap is not consistent across processors. Rather than holding (via a lock) processors until this value is set and then flushing the cache so that all processors see the same value, this solution moves the code such that all processors set it, thus maintaining parallelism and keeping the code simple. Change-Id: I2e5385c47124adcd99803337167984b6307af860 Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55629 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/security/intel/stm/StmPlatformSmm.c 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c index 248ccc0..3f29afc 100644 --- a/src/security/intel/stm/StmPlatformSmm.c +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -173,12 +173,15 @@ return; } + // This code moved here because paralled SMM setup can cause some + // processors to get a bad value. + addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; + stm_resource_heap = (uint8_t *) addr_calc; + if (cpu == 0) { // need to create the BIOS resource list once // first calculate the location in SMRAM - addr_calc = mseg - CONFIG_BIOS_RESOURCE_LIST_SIZE; - stm_resource_heap = (uint8_t *) addr_calc; printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", stm_resource_heap); //setup the the list -- To view, visit https://review.coreboot.org/c/coreboot/+/55629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I2e5385c47124adcd99803337167984b6307af860 Gerrit-Change-Number: 55629 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[4.11_branch]: security/intel/stm: Make sure stm_resource_heap is consistent
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55629?usp=email ) Change subject: security/intel/stm: Make sure stm_resource_heap is consistent ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I2e5385c47124adcd99803337167984b6307af860 Gerrit-Change-Number: 55629 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:21:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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