coreboot-gerrit June 2023

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[S] Change in coreboot[4.11_branch]: cpu/x86/: Centralize MSEG location calculation
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55628?usp=email ) Change subject: cpu/x86/: Centralize MSEG location calculation ...................................................................... cpu/x86/: Centralize MSEG location calculation This patch centralizes the MSEG location calculation. In the current implementation, the calculation happens in smm_module_loader and mp_init. When smm_module_loaderv2 was added, this calculation became broken as the original calculation made assumptions based on perm_smbase. The calculation is now located in smm_subregion (tseg_region.c), as the MSEG is located within the TSEG (or SMM); These patches have been tested on a Purism librem-l1um server. Change-Id: Ic17e1a505401c3b2a218826dffae6fe12a5c15c6 Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55628 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_module_loaderv2.c M src/cpu/x86/smm/tseg_region.c M src/include/cpu/x86/smm.h 5 files changed, 20 insertions(+), 8 deletions(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 57b8865..313fb34 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -756,9 +756,9 @@ if (CONFIG(STM)) { if (is_smm_enabled()) { uintptr_t mseg; + size_t mseg_size; - mseg = mp_state.perm_smbase + - (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + smm_subregion(SMM_SUBREGION_MSEG, &mseg, &mseg_size); stm_setup(mseg, p->cpu, runtime->num_cpus, perm_smbase, diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 19acea6..dd00b7f 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -368,7 +368,7 @@ base += size; if (CONFIG(STM)) - base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + base -= CONFIG_BIOS_RESOURCE_LIST_SIZE; params->stack_top = base; diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index 04654f7..8d01b3c 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -586,8 +586,8 @@ /* MSEG starts at the top of SMRAM and works down */ if (CONFIG(STM)) { - base -= CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; - total_size += CONFIG_MSEG_SIZE + CONFIG_BIOS_RESOURCE_LIST_SIZE; + base -= CONFIG_BIOS_RESOURCE_LIST_SIZE; + total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; } /* FXSAVE goes below MSEG */ diff --git a/src/cpu/x86/smm/tseg_region.c b/src/cpu/x86/smm/tseg_region.c index a8b8bb7..747dacd 100644 --- a/src/cpu/x86/smm/tseg_region.c +++ b/src/cpu/x86/smm/tseg_region.c @@ -17,6 +17,7 @@ #include <cpu/x86/smm.h> #include <stage_cache.h> #include <types.h> +#include <inttypes.h> /* * Subregions within SMM @@ -25,6 +26,8 @@ * +-------------------------+ * | External Stage Cache | SMM_RESERVED_SIZE * +-------------------------+ + * | STM | MSEG_SIZE + * +-------------------------+ * | code and data | * | (TSEG) | * +-------------------------+ TSEG @@ -35,17 +38,24 @@ size_t sub_size; const size_t ied_size = CONFIG_IED_REGION_SIZE; const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + const size_t mseg_size = CONFIG_MSEG_SIZE; smm_region(&sub_base, &sub_size); ASSERT(IS_ALIGNED(sub_base, sub_size)); - ASSERT(sub_size > (cache_size + ied_size)); + ASSERT(sub_size > (cache_size + ied_size + mseg_size)); switch (sub) { case SMM_SUBREGION_HANDLER: /* Handler starts at the base of TSEG. */ sub_size -= ied_size; sub_size -= cache_size; + sub_size -= mseg_size; + break; + case SMM_SUBREGION_MSEG: + /* MSEG follows the SMM HANDLER subregion */ + sub_base += sub_size - (ied_size + cache_size + mseg_size); + sub_size = mseg_size; break; case SMM_SUBREGION_CACHE: /* External cache is in the middle of TSEG. */ @@ -88,11 +98,11 @@ return; printk(BIOS_DEBUG, "SMM Memory Map\n"); - printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size); + printk(BIOS_DEBUG, "SMRAM : 0x%" PRIxPTR " 0x%zx\n", base, size); for (i = 0; i < SMM_SUBREGION_NUM; i++) { if (smm_subregion(i, &base, &size)) continue; - printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size); + printk(BIOS_DEBUG, " Subregion %d: 0x%" PRIxPTR " 0x%zx\n", i, base, size); } } diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index d8f6d0e..b449296 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -168,6 +168,8 @@ enum { /* SMM handler area. */ SMM_SUBREGION_HANDLER, + /* MSEG (STM). */ + SMM_SUBREGION_MSEG, /* SMM cache region. */ SMM_SUBREGION_CACHE, /* Chipset specific area. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ic17e1a505401c3b2a218826dffae6fe12a5c15c6 Gerrit-Change-Number: 55628 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[4.11_branch]: cpu/x86/: Centralize MSEG location calculation
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55628?usp=email ) Change subject: cpu/x86/: Centralize MSEG location calculation ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ic17e1a505401c3b2a218826dffae6fe12a5c15c6 Gerrit-Change-Number: 55628 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:21:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: security/intel/stm: Reset BIOS resource list on every stm_setup call
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55627?usp=email ) Change subject: security/intel/stm: Reset BIOS resource list on every stm_setup call ...................................................................... security/intel/stm: Reset BIOS resource list on every stm_setup call Some platforms run the smm_relocation function twice during initialization. This results in the BIOS resource list becoming twice as long. Also, testing has shown that elements of the list created in the first interation may have invalid data included in the resource list. This patch resolves these issues by reseting the list every time stm_setup is involked. This patch has been tested on the Purism L1UM-1X8C Change-Id: I874871ff01bdf0d00a3e6b48bc885e7abaa25112 Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55627 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/security/intel/stm/StmPlatformResource.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c index 6fef515..7aa432d 100644 --- a/src/security/intel/stm/StmPlatformResource.c +++ b/src/security/intel/stm/StmPlatformResource.c @@ -179,8 +179,12 @@ /* * Add resources to BIOS resource database. */ + +extern uint8_t *m_stm_resources_ptr; + void add_resources_cmd(void) { + m_stm_resources_ptr = NULL; add_simple_resources(); -- To view, visit https://review.coreboot.org/c/coreboot/+/55627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I874871ff01bdf0d00a3e6b48bc885e7abaa25112 Gerrit-Change-Number: 55627 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[4.11_branch]: security/intel/stm: Reset BIOS resource list on every stm_setup call
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55627?usp=email ) Change subject: security/intel/stm: Reset BIOS resource list on every stm_setup call ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I874871ff01bdf0d00a3e6b48bc885e7abaa25112 Gerrit-Change-Number: 55627 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:20:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: Enable STM for broadwell_de
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55626?usp=email ) Change subject: soc/intel/fsp_broadwell_de: Enable STM for broadwell_de ...................................................................... soc/intel/fsp_broadwell_de: Enable STM for broadwell_de This patch enables the STM for broadwell_de by setting CONFIG_VMX Change-Id: I8292bb4eec516556ad1ba658c80ad8a0b541139f Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/soc/intel/fsp_broadwell_de/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 0186e85..17a15f6 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -95,6 +95,10 @@ hex default 0x80 +config ENABLE_VMX + bool "Enable VMX for virtualization" + default y + ## Broadwell-DE Specific FSP Kconfig source src/soc/intel/fsp_broadwell_de/fsp/Kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/55626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I8292bb4eec516556ad1ba658c80ad8a0b541139f Gerrit-Change-Number: 55626 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[4.11_branch]: soc/intel/fsp_broadwell_de: Enable STM for broadwell_de
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers, Patrick Rudolph. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55626?usp=email ) Change subject: soc/intel/fsp_broadwell_de: Enable STM for broadwell_de ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I8292bb4eec516556ad1ba658c80ad8a0b541139f Gerrit-Change-Number: 55626 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:20:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: 3rdparty: Add STM as a submodule
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55625?usp=email ) Change subject: 3rdparty: Add STM as a submodule ...................................................................... 3rdparty: Add STM as a submodule The patch incorporates the STM build as a part of the coreboot build. A separate patch lists and documents the options that the developer can use. In most cases the default options will suffice. Original-Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796 Original-Signed-off-by: Eugene D Myers <cedarhouse(a)comcast.net> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: ron minnich <rminnich(a)gmail.com> Change-Id: I901cb429d8050fb2a7c839e8ef29ac3359239d2c Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55625 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M .gitmodules 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/.gitmodules b/.gitmodules index 1b47275..14782d4 100644 --- a/.gitmodules +++ b/.gitmodules @@ -43,3 +43,7 @@ url = ../amd_blobs update = none ignore = dirty +[submodule "3rdparty/stm"] + path = 3rdparty/stm + url = ../STM + branch = stmpe -- To view, visit https://review.coreboot.org/c/coreboot/+/55625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I901cb429d8050fb2a7c839e8ef29ac3359239d2c Gerrit-Change-Number: 55625 Gerrit-PatchSet: 3 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[4.11_branch]: 3rdparty: Add STM as a submodule
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55625?usp=email ) Change subject: 3rdparty: Add STM as a submodule ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I901cb429d8050fb2a7c839e8ef29ac3359239d2c Gerrit-Change-Number: 55625 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:20:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: security/intel/stm/SmmStm.c: Fix size_t printf format error
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55623?usp=email ) Change subject: security/intel/stm/SmmStm.c: Fix size_t printf format error ...................................................................... security/intel/stm/SmmStm.c: Fix size_t printf format error Replaced the 'l' with a 'z' to clear up the issue. Change-Id: I696b615b4dd3bacda7151c91fff17f9b01b17821 Signed-off-by: Eugene Myers <edmyers(a)tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55623 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/intel/stm/SmmStm.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Stefan Reinauer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index f23be70..523a63f 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -490,7 +490,7 @@ return -1; // INVALID_PARAMETER; resource_size = get_resource_size(resource_list, num_entries); - printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08lx\n", resource_size); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08x\n", (int) resource_size); if (resource_size == 0) return -1; // INVALID_PARAMETER; -- To view, visit https://review.coreboot.org/c/coreboot/+/55623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I696b615b4dd3bacda7151c91fff17f9b01b17821 Gerrit-Change-Number: 55623 Gerrit-PatchSet: 2 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[4.11_branch]: security/intel/stm/SmmStm.c: Fix size_t printf format error
by Stefan Reinauer (Code Review) 10 Jun '23

10 Jun '23

Attention is currently required from: Eugene Myers. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55623?usp=email ) Change subject: security/intel/stm/SmmStm.c: Fix size_t printf format error ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I696b615b4dd3bacda7151c91fff17f9b01b17821 Gerrit-Change-Number: 55623 Gerrit-PatchSet: 1 Gerrit-Owner: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eugene Myers <cedarhouse1(a)comcast.net> Gerrit-Comment-Date: Sat, 10 Jun 2023 03:20:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2023