coreboot-gerrit June 2023

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 5: (2 comments) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/4cfc2457_50bd4286 : PS5, Line 263: if (code >= 0x01 && code <= 0x23) : return type[code - 0x01]; : return "Unsupported memory type"; > WDYT? […] Any improvement or help? TBH, I copied this function from dmi_decode upstream. And I am considering remove the DDR below DDR4. https://review.coreboot.org/c/coreboot/+/75756/comment/6f21be40_3a91f294 : PS5, Line 1046: > i would have called below func from here […] b/c this would need check many things if empty slot. so I add in create_smbios_type17_for_dimm. no need to print empty dimms. -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 12 Jun 2023 11:27:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Sridhar Siricilla (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kapil Porwal, Meera Ravindranath, Paul Menzel, Ronak Kanabar, Subrata Banik, Tarun Tuli. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/75663/comment/539ee0a3_e86d22aa : PS4, Line 208: #error You need to implement this struct for x86_64 FSP : #endif : > > Please refer them in the same file […] Ideally, it should go there, but if we want to try out 32 bit bootloader, then we will miss the flexibility when FSP 2.4 spec is enabled. Hence, I am suggesting outside of *x86_32 flag. Also, we can remove *x86_32 flag from this file also clears the air. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 11:25:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by 9elements QA (Code Review) 12 Jun '23

12 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 14 / 1 / 15 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/168842 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/168840 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/168839 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/168838 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/168837 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/168836 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/168835 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/168834 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/168833 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/168832 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/168831 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/168830 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/168829 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/168828 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/168827 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 11:21:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Lean Sheng Tan (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Kyösti Mälkki, Lance Zhao, Nico Huber, Paul Menzel, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 11:15:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vc/intel/fsp/fsp20/meteorlake: Add VR config entries
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75761?usp=email ) Change subject: vc/intel/fsp/fsp20/meteorlake: Add VR config entries ...................................................................... vc/intel/fsp/fsp20/meteorlake: Add VR config entries This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h 1 file changed, 74 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/75761/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h index f8edff8..aacb42a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h @@ -1433,7 +1433,35 @@ /** Offset 0x06B4 - Reserved **/ - UINT8 Reserved33[336]; + UINT8 Reserved33[166]; + +/** Offset 0x075A - VR Fast Vmode ICC Limit support + Voltage Regulator Fast Vmode ICC Limit. A value of 400 = 100A. A value of 0 corresponds + to feature disabled (no reactive protection). This value represents the current + threshold where the VR would initiate reactive protection if Fast Vmode is enabled. + The value is represented in 1/4 A increments. Range 0-2040. [0] for IA, [1] for + GT, [2] for SA, [3] through [5] are Reserved. +**/ + UINT16 IccLimit[6]; + +/** Offset 0x0766 - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled. + Enable/Disable VR FastVmode; [0] for IA, [1] for GT, 0: Disable; 1: Enable. + [2] for SA, 0: Disable; 1: Enable. + 0: Disable, 1: Enable +**/ + UINT8 EnableFastVmode[6]; + +/** Offset 0x076C - Enable CEP + Enable/Disable CEP (Current Excursion Protection) Support. [0] for IA, [1] for GT, + 0: Disable; 1: Enable. [2] for SA, 0: Disable; 1: Enable. [3] through + [5] are Reserved. + $EN_DIS +**/ + UINT8 CepEnable[6]; + +/** Offset 0x0772 - Reserved +**/ + UINT8 Reserved34[146]; /** Offset 0x0804 - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1455,7 +1483,7 @@ /** Offset 0x0807 - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved35; /** Offset 0x0808 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1469,7 +1497,7 @@ /** Offset 0x0810 - Reserved **/ - UINT8 Reserved35[8]; + UINT8 Reserved36[8]; /** Offset 0x0818 - TxtDprMemoryBase Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable @@ -1524,7 +1552,7 @@ /** Offset 0x0849 - Reserved **/ - UINT8 Reserved36[32]; + UINT8 Reserved37[32]; /** Offset 0x0869 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1711,7 +1739,7 @@ /** Offset 0x0A85 - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved38; /** Offset 0x0A86 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1731,7 +1759,7 @@ /** Offset 0x0A99 - Reserved **/ - UINT8 Reserved38[16]; + UINT8 Reserved39[16]; /** Offset 0x0AA9 - SOC/IOE ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -1740,7 +1768,7 @@ /** Offset 0x0AB9 - Reserved **/ - UINT8 Reserved39[55]; + UINT8 Reserved40[55]; /** Offset 0x0AF0 - Enable PCH PCIE RP Mask Enable/disable PCH PCIE Root Ports. 0: disable, 1: enable. One bit for each port, @@ -1792,7 +1820,7 @@ /** Offset 0x0AFE - Reserved **/ - UINT8 Reserved40[2]; + UINT8 Reserved41[2]; /** Offset 0x0B00 - DMIC<N> ClkA Pin Muxing (N - DMIC number) Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* @@ -1812,7 +1840,7 @@ /** Offset 0x0B11 - Reserved **/ - UINT8 Reserved41[3]; + UINT8 Reserved42[3]; /** Offset 0x0B14 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -1837,7 +1865,7 @@ /** Offset 0x0B27 - Reserved **/ - UINT8 Reserved42; + UINT8 Reserved43; /** Offset 0x0B28 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T @@ -1853,7 +1881,7 @@ /** Offset 0x0B2A - Reserved **/ - UINT8 Reserved43[6]; + UINT8 Reserved44[6]; /** Offset 0x0B30 - CNVi DDR RFI Mitigation Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE @@ -1863,7 +1891,7 @@ /** Offset 0x0B31 - Reserved **/ - UINT8 Reserved44[11]; + UINT8 Reserved45[11]; /** Offset 0x0B3C - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1885,7 +1913,7 @@ /** Offset 0x0B3F - Reserved **/ - UINT8 Reserved45; + UINT8 Reserved46; /** Offset 0x0B40 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -1913,7 +1941,7 @@ /** Offset 0x0B47 - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved47; /** Offset 0x0B48 - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -1929,7 +1957,7 @@ /** Offset 0x0B4D - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved48; /** Offset 0x0B4E - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -1943,7 +1971,7 @@ /** Offset 0x0B50 - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved49; /** Offset 0x0B51 - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-15 @@ -2061,7 +2089,7 @@ /** Offset 0x0B64 - Reserved **/ - UINT8 Reserved49; + UINT8 Reserved50; /** Offset 0x0B65 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D @@ -2089,7 +2117,7 @@ /** Offset 0x0B69 - Reserved **/ - UINT8 Reserved50[10]; + UINT8 Reserved51[10]; /** Offset 0x0B73 - Read Equalization Training Enables/Disable Read Equalization Training @@ -2099,7 +2127,7 @@ /** Offset 0x0B74 - Reserved **/ - UINT8 Reserved51[2]; + UINT8 Reserved52[2]; /** Offset 0x0B76 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D @@ -2127,7 +2155,7 @@ /** Offset 0x0B7A - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved53; /** Offset 0x0B7B - Command Voltage Centering Enables/Disable Command Voltage Centering @@ -2155,7 +2183,7 @@ /** Offset 0x0B7F - Reserved **/ - UINT8 Reserved53; + UINT8 Reserved54; /** Offset 0x0B80 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test @@ -2171,7 +2199,7 @@ /** Offset 0x0B82 - Reserved **/ - UINT8 Reserved54; + UINT8 Reserved55; /** Offset 0x0B83 - Dimm ODT Training Enables/Disable Dimm ODT Training @@ -2205,7 +2233,7 @@ /** Offset 0x0B88 - Reserved **/ - UINT8 Reserved55[2]; + UINT8 Reserved56[2]; /** Offset 0x0B8A - DIMM CA ODT Training Enable/Disable DIMM CA ODT Training @@ -2215,7 +2243,7 @@ /** Offset 0x0B8B - Reserved **/ - UINT8 Reserved56[3]; + UINT8 Reserved57[3]; /** Offset 0x0B8E - Read Vref Decap Training Enable/Disable Read Vref Decap Training @@ -2237,7 +2265,7 @@ /** Offset 0x0B91 - Reserved **/ - UINT8 Reserved57[4]; + UINT8 Reserved58[4]; /** Offset 0x0B95 - Duty Cycle Correction Training Enable/Disable Duty Cycle Correction Training @@ -2247,7 +2275,7 @@ /** Offset 0x0B96 - Reserved **/ - UINT8 Reserved58[17]; + UINT8 Reserved59[17]; /** Offset 0x0BA7 - ECC Support Enables/Disable ECC Support @@ -2281,7 +2309,7 @@ /** Offset 0x0BB3 - Reserved **/ - UINT8 Reserved59; + UINT8 Reserved60; /** Offset 0x0BB4 - IbeccProtectedRegionBases IBECC Protected Region Bases per IBECC instance @@ -2361,7 +2389,7 @@ /** Offset 0x0BEE - Reserved **/ - UINT8 Reserved60; + UINT8 Reserved61; /** Offset 0x0BEF - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2371,7 +2399,7 @@ /** Offset 0x0BF0 - Reserved **/ - UINT8 Reserved61[4]; + UINT8 Reserved62[4]; /** Offset 0x0BF4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP @@ -2630,7 +2658,7 @@ /** Offset 0x0C2B - Reserved **/ - UINT8 Reserved62[2]; + UINT8 Reserved63[2]; /** Offset 0x0C2D - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2650,7 +2678,7 @@ /** Offset 0x0C30 - Reserved **/ - UINT8 Reserved63; + UINT8 Reserved64; /** Offset 0x0C31 - Energy Performance Gain Enable/disable Energy Performance Gain. 0: Disable; 1: Enable @@ -2660,7 +2688,7 @@ /** Offset 0x0C32 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved65; /** Offset 0x0C33 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2678,7 +2706,7 @@ /** Offset 0x0C35 - Reserved **/ - UINT8 Reserved65; + UINT8 Reserved66; /** Offset 0x0C36 - Power Down Mode This option controls command bus tristating during idle periods @@ -2715,7 +2743,7 @@ /** Offset 0x0C3B - Reserved **/ - UINT8 Reserved66[8]; + UINT8 Reserved67[8]; /** Offset 0x0C43 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. @@ -2730,7 +2758,7 @@ /** Offset 0x0C45 - Reserved **/ - UINT8 Reserved67; + UINT8 Reserved68; /** Offset 0x0C46 - Post Code Output Port This option configures Post Code Output Port @@ -2750,7 +2778,7 @@ /** Offset 0x0C4A - Reserved **/ - UINT8 Reserved68[2]; + UINT8 Reserved69[2]; /** Offset 0x0C4C - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2793,7 +2821,7 @@ /** Offset 0x0C62 - Reserved **/ - UINT8 Reserved69[13]; + UINT8 Reserved70[13]; /** Offset 0x0C6F - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller @@ -2809,7 +2837,7 @@ /** Offset 0x0C71 - Reserved **/ - UINT8 Reserved70[24]; + UINT8 Reserved71[24]; /** Offset 0x0C89 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2845,7 +2873,7 @@ /** Offset 0x0C8E - Reserved **/ - UINT8 Reserved71[2]; + UINT8 Reserved72[2]; /** Offset 0x0C90 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -2859,7 +2887,7 @@ /** Offset 0x0C95 - Reserved **/ - UINT8 Reserved72[143]; + UINT8 Reserved73[143]; /** Offset 0x0D24 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -2875,7 +2903,7 @@ /** Offset 0x0D28 - Reserved **/ - UINT8 Reserved73[28]; + UINT8 Reserved74[28]; /** Offset 0x0D44 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -2891,7 +2919,7 @@ /** Offset 0x0D46 - Reserved **/ - UINT8 Reserved74[2]; + UINT8 Reserved75[2]; /** Offset 0x0D48 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write @@ -2902,7 +2930,7 @@ /** Offset 0x0D49 - Reserved **/ - UINT8 Reserved75[34]; + UINT8 Reserved76[34]; /** Offset 0x0D6B - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI @@ -2955,7 +2983,7 @@ /** Offset 0x0D73 - Reserved **/ - UINT8 Reserved76[100]; + UINT8 Reserved77[100]; /** Offset 0x0DD7 - Avx2 Voltage Guardband Scaling Factor AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in @@ -2978,7 +3006,7 @@ /** Offset 0x0DDA - Reserved **/ - UINT8 Reserved77[2]; + UINT8 Reserved78[2]; /** Offset 0x0DDC - SerialIoUartDebugRxPinMux - FSPM Select RX pin muxing for SerialIo UART used for debug @@ -3004,7 +3032,7 @@ /** Offset 0x0DEC - Reserved **/ - UINT8 Reserved78[188]; + UINT8 Reserved79[188]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/75761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Gerrit-Change-Number: 75761 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kapil Porwal, Meera Ravindranath, Paul Menzel, Ronak Kanabar, Sridhar Siricilla, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/75663/comment/9537f3f4_d82fa5a7 : PS4, Line 208: #error You need to implement this struct for x86_64 FSP : #endif : > Please refer them in the same file > https://review.coreboot.org/c/coreboot/+/75663/4/src/vendorcode/intel/edk2/… > > @https://review.coreboot.org/c/coreboot/+/75663/4/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h#256 > > https://review.coreboot.org/c/coreboot/+/75663/4/src/vendorcode/intel/edk2/… in that case, we need to add `FSPM_ARCH2_UPD` inside the #else block -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:59:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Sridhar Siricilla (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kapil Porwal, Meera Ravindranath, Paul Menzel, Ronak Kanabar, Subrata Banik, Tarun Tuli. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/75663/comment/f4eaacbf_be012da3 : PS4, Line 208: #error You need to implement this struct for x86_64 FSP : #endif : > > This is not required any more as FSPM_ARCH2_UPD/ FSPS_ARCH2_UPD/FSPT_ARCH2_UPD declaration reflect […] Please refer them in the same file https://review.coreboot.org/c/coreboot/+/75663/4/src/vendorcode/intel/edk2/… @https://review.coreboot.org/c/coreboot/+/75663/4/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h#256 https://review.coreboot.org/c/coreboot/+/75663/4/src/vendorcode/intel/edk2/… -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:51:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/variants/ovis: Add display configuration
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Jakub Czapiga, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75579?usp=email ) Change subject: mb/google/rex/variants/ovis: Add display configuration ...................................................................... Patch Set 5: Code-Review+1 (2 comments) File src/mainboard/google/rex/variants/ovis/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75579/comment/bceed482_cf04a20c : PS1, Line 17: register "ddi_port_A_config" = "0" : register "ddi_port_B_config" = "0" > u can drop this Acknowledged File src/mainboard/google/rex/variants/ovis/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75579/comment/d70cd1c4_2e9d813e : PS5, Line 184: device ref ipu on end can we submit a separate CL for this ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40f967b12b11c10a1a9329bfb42ebec5a8d7738f Gerrit-Change-Number: 75579 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Arthur Heymans (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Benjamin Doron, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Nico Huber, Paul Menzel, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 7: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75677/comment/95555b77_9854fbac : PS6, Line 1864: } else if ((all_zero == 2) || (all_one == 2)) { : printk(BIOS_SPEW, "...\n"); : } > Looking into `acpixtract`, it seems to completely ignore the offsets. > So, yeah, nothing but printing every single byte will work directly. > Alternatively, one could run the data through a better hexdump parser, > but meh, not everybody has `xxd` installed. > > Btw. it looks like we don't need the "%c" part. It seems to just look for > ` .*:( *[0-9A-F]{2}){16}` and discards the rest. acpidump from ACPICA does also generate that %c part. -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:48:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/variants/ovis: Add basic DTT
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Paul Menzel, Sumeet R Pawnikar, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75580?usp=email ) Change subject: mb/google/rex/variants/ovis: Add basic DTT ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75580/comment/b60a1d4c_87609638 : PS5, Line 8: > Please add a line to the commit message body. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Gerrit-Change-Number: 75580 Gerrit-PatchSet: 6 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:48:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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