coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/myst: Update PCIe romstage gpios
by Jon Murphy (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Karthik Ramasubramanian, Martin Roth, Tim Van Patten. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75699?usp=email ) Change subject: mb/google/myst: Update PCIe romstage gpios ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/myst/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/75699/comment/43f06cf3_e72b7be6 : PS2, Line 207: CLK_REQ3_L > Why only CLK_REQ for SSD and not WLAN, SD. The SSD clock request line is required before PCIe link training. I don't have strong feelings about enabling the others, but this is the same thing we did on Skyrim -- To view, visit https://review.coreboot.org/c/coreboot/+/75699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Gerrit-Change-Number: 75699 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:35:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
by Ziang Wang (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu. Ziang Wang has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor ...................................................................... Removed Code-Review+2 by Eric Lai <eric_lai(a)quanta.corp-partner.google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 7 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: deleteVote

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
by Ziang Wang (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu. Ziang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor ...................................................................... Patch Set 7: Code-Review-1 (1 comment) Patchset: PS7: > Would be 4 and 6 are choosable? If so, use Kconfig and prove the select. If not LGTM now. Wait you actually reminded me... though now most SPR SKUs support persistent memory, there are some SKUs that do not, and hence support only 4TB mem capacity. I think it's better using a mainboard overrider or Kconfig here...let me discuss with the patch owner. -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 7 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:22:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kapil Porwal, Meera Ravindranath, Paul Menzel, Ronak Kanabar, Sridhar Siricilla, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/75663/comment/8efc7f17_e595f182 : PS4, Line 208: #error You need to implement this struct for x86_64 FSP : #endif : > > Ideally, it should go there, but if we want to try out 32 bit bootloader, then we will miss the flexibility when FSP 2.4 spec is enabled. Hence, I am suggesting outside of *x86_32 flag. Also, we can remove *x86_32 flag from this file also clears the air. WDYT? > > Coreboot can run in 64bit mode with a 32bit FSP by dropping to 32bit mode before calling FSP. You want to make sure that PLATFORM_USES_FSP2_X86_32 is selected when that is the case which is what this error achieves. I guess that FSP mode can be parses from the header on newer revisions? Maybe you can move this error message from C code to makefile? looking at edk2-stable202305 source code, I still feel the need to have `PLATFORM_USES_FSP2_X86_32` pre-processor check as is. https://github.com/tianocore/edk2/blob/edk2-stable202305/IntelFsp2Pkg/Inclu… due to having variable size field in the EDK2 header file, we are running into the issue while compiling FSP in 32bit (note: coreboot and FSP both are in 32bit). details : https://github.com/intel/FSP/issues/59 we shall first try to fix this problem and then think about migrating to 64-bit FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:21:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
by Matt DeVillier (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Jason Nien, Karthik Ramasubramanian, Martin Roth, Paul Menzel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75698?usp=email ) Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75698/comment/122c1ed2_81af054e : PS2, Line 18: uses already uses > One *uses* should be enough. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75698?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Gerrit-Change-Number: 75698 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:11:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add basic DTT
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Paul Menzel, Sumeet R Pawnikar, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75580?usp=email ) Change subject: mb/google/rex/variants/ovis: Add basic DTT ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Gerrit-Change-Number: 75580 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:09:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB and TCSS configuration
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75578?usp=email ) Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration ...................................................................... Patch Set 7: (4 comments) File src/mainboard/google/rex/variants/ovis/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75578/comment/213280fc_4296f70f : PS7, Line 138: CENTER we already have `front, center` for Type-C 0 ideally Type-A1 can be either `top` or `bottom` https://review.coreboot.org/c/coreboot/+/75578/comment/31585ca5_ce9b796f : PS7, Line 145: 4, 1 shouldn't this be 3, 3? https://review.coreboot.org/c/coreboot/+/75578/comment/d29c414c_68612a2f : PS7, Line 152: (4, 2) 3, 4 ? https://review.coreboot.org/c/coreboot/+/75578/comment/5637ab60_edecb110 : PS7, Line 166: CENTER either top or bottom may be ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:08:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 6: (1 comment) File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/75756/comment/446bca89_9a72d619 : PS5, Line 362: config DUMP_SMBIOS_TYPE17 : bool : default n : help : Dump part of SMBIOS type17 dimm information > > Do you mean select by menu? Do you want to add choice on this? I am fine with that. […] IMHO, we already have SPD dump print, information are duplicated. This is useful for DDR5 for now. So I am hesitate to open it XD -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 6 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 12 Jun 2023 12:02:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add basic DTT
by Jakub Czapiga (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli. Hello Eric Lai, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75580?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/google/rex/variants/ovis: Add basic DTT ...................................................................... mb/google/rex/variants/ovis: Add basic DTT Add default Intel DPTF. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75580/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Gerrit-Change-Number: 75580 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB and TCSS configuration
by Jakub Czapiga (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75578?usp=email to look at the new patch set (#8). Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration ...................................................................... mb/google/rex/variants/ovis: Add USB and TCSS configuration +-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 156 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75578/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 8 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2023