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Change subject: mb/google/rex: Set FVM configuration for MTL-P 28W
......................................................................
mb/google/rex: Set FVM configuration for MTL-P 28W
This patch sets the FVM configuration parameter as suggested in Intel
doc 640982. As per the doc, Intel MTL-P 28W CPU supports FVM on IA, GT
and SA.
The baseline Icc max for IA is 93A, 53A for GT and 35A for SA.
BUG=b:286809233
TEST=Able to build and boot google/rex without seeing any performance
regression.
Change-Id: If834c1af8141a19fd2daae653579225b77cfa6c8
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/75764/1
diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
index 9a71e95..d776450 100644
--- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
@@ -53,6 +53,21 @@
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
+ # As per doc 640982, Intel MTL-P 28W CPU supports FVM on IA, GT and SA
+ # The ICC Limit is represented in 1/4 A increments, i.e., A value of 400 = 100A
+ # For IA VR configuration
+ register "enable_fast_vmode[VR_DOMAIN_IA]" = "1"
+ register "cep_enable[VR_DOMAIN_IA]" = "1"
+ register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "372" # 93A
+ # For GT VR configuration
+ register "enable_fast_vmode[VR_DOMAIN_GT]" = "1"
+ register "cep_enable[VR_DOMAIN_GT]" = "1"
+ register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "212" # 53A
+ # For SA VR configuration
+ register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"
+ register "cep_enable[VR_DOMAIN_SA]" = "1"
+ register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "140" # 35A
+
device domain 0 on
device ref igpu on end
device ref dtt on end
--
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Change subject: mb/google/rex: Set FVM configuration for MTL-U 15W
......................................................................
mb/google/rex: Set FVM configuration for MTL-U 15W
This patch sets the FVM configuration parameter as suggested in Intel
doc 640982. As per the doc, Intel MTL-U 15W CPU supports FVM on IA and
SA.
The baseline Icc max for IA is 72A and 35A for SA.
BUG=b:286809233
TEST=Able to build and boot google/rex without seeing any performance
regression.
Change-Id: Ia7157bddf2e9586e4a91cc55e48693561072cd05
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/75763/1
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index bd5b0bb..be66485 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -67,6 +67,17 @@
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_codec_enable" = "1"
+ # As per doc 640982, Intel MTL-U 15W CPU supports FVM on IA and SA
+ # The ICC Limit is represented in 1/4 A increments, i.e., A value of 400 = 100A
+ # For IA VR configuration
+ register "enable_fast_vmode[VR_DOMAIN_IA]" = "1"
+ register "cep_enable[VR_DOMAIN_IA]" = "1"
+ register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "288" # 72A
+ # For SA VR configuration
+ register "enable_fast_vmode[VR_DOMAIN_SA]" = "1"
+ register "cep_enable[VR_DOMAIN_SA]" = "1"
+ register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "140" # 35A
+
device domain 0 on
device ref igpu on end
device ref dtt on end
--
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The following approvals got outdated and were removed:
Code-Review-1 by Jay Patel
Change subject: soc/intel/meteorlake: Add provision to override the Fast Vmode
......................................................................
soc/intel/meteorlake: Add provision to override the Fast Vmode
This patch adds option to override Fast Vmode on Meteor Lake SoC.
This requires CepEnable, EnableFastVmode, IccLimit FSPM UPDs in FSP
header. If the hardware supports Fast Vmode, the FSPM will set the
ICC limit value to the value passed from coreboot.
If no value is passed by coreboot and FSPM will set it to default
value.
BUG=b:286809233
TEST=In debug MTL FSP logs, the value of FSP parameters is as passed
from coreboot including enable_fast_vmode, cep_enable, and
fast_vmode_i_trip. Also, fast_vmode_i_trip value is passed to
pcode using mailbox command without any error. This test done
on google/rex board.
Signed-off-by: Jay Patel <jay2.patel(a)intel.com>
Change-Id: Id05dccac56c504523f9327babe0c6fbeff488ec2
---
M src/soc/intel/meteorlake/chip.h
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/75566/2
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
I'll check the device tomorrow.
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/0a0e82ed_9712d773 :
PS2, Line 207: CLK_REQ3_L
> Not required. […]
Done
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Change subject: mb/google/nissa/var/joxer: enable ELAN and G2touch touchscreen
......................................................................
Patch Set 1:
This change is ready for review.
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Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration
......................................................................
Patch Set 9: Code-Review+2
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Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration
......................................................................
Patch Set 9:
(5 comments)
File src/mainboard/google/rex/variants/ovis/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75578/comment/8b30c20c_27d5b73b :
PS6, Line 64: RIGHT
> I changed it to reflect order of connections on Ovis baseplate. […]
Done
File src/mainboard/google/rex/variants/ovis/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75578/comment/0d936d66_1091a623 :
PS7, Line 138: CENTER
> we already have `front, center` for Type-C 0 […]
Done
https://review.coreboot.org/c/coreboot/+/75578/comment/a0b1b815_188e5860 :
PS7, Line 145: 4, 1
> shouldn't this be 3, 3?
Done
https://review.coreboot.org/c/coreboot/+/75578/comment/331b342e_0001c326 :
PS7, Line 152: (4, 2)
> 3, 4 ?
Done
https://review.coreboot.org/c/coreboot/+/75578/comment/fa502ac7_277bf85a :
PS7, Line 166: CENTER
> either top or bottom may be ?
Done
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