coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD
by Nick Vaccaro (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: David Wu, Lucas Chen, Tarun Tuli, YH Lin. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75745?usp=email ) Change subject: mb/google/brya/var/osiris: Add Micron MT53E2G32D4NQ-046 WT:C SPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c66a18fd94d9a013710fbc6dc7f1533d808392e Gerrit-Change-Number: 75745 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 16:07:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB and TCSS configuration
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75578?usp=email ) Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 11 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 16:06:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB and TCSS configuration
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75578?usp=email ) Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration ...................................................................... Patch Set 11: (1 comment) File src/mainboard/google/rex/variants/ovis/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75578/comment/c6f6f6a0_e280b1e0 : PS10, Line 137: BOTTOM, CENTER, > I changed C0 and A2 to same Panel nad Horizontal position and added vertical position to both of the […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 11 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 16:06:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB and TCSS configuration
by Jakub Czapiga (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Kapil Porwal, Subrata Banik, Tarun Tuli. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75578?usp=email ) Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration ...................................................................... Patch Set 10: (2 comments) File src/mainboard/google/rex/variants/ovis/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75578/comment/ae90c7ce_a4de8c40 : PS10, Line 137: BOTTOM, CENTER, > IMO, the horizontal alignment could be `front/back` or 'left/center/right` and vertical alignment wo […] I changed C0 and A2 to same Panel nad Horizontal position and added vertical position to both of them. (default is UPPER). https://review.coreboot.org/c/coreboot/+/75578/comment/b7df2a3c_92aecc24 : PS10, Line 165: ACPI_PLD_TYPE_A(FRONT, BOTTOM, ACPI_PLD_GROUP(3, 2)) > need to align with patchset 10? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 10 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 15:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB and TCSS configuration
by Jakub Czapiga (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75578?usp=email to look at the new patch set (#11). Change subject: mb/google/rex/variants/ovis: Add USB and TCSS configuration ...................................................................... mb/google/rex/variants/ovis: Add USB and TCSS configuration +-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 160 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75578/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 11 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/mediatek/mt8188: Support 4K resolution display
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75661?usp=email ) Change subject: soc/mediatek/mt8188: Support 4K resolution display ...................................................................... soc/mediatek/mt8188: Support 4K resolution display The original clock rate 416MHz is insufficient for 4K resolution and causing the screen to glitch. Set the clock rate to 594MHz to support 4K resolution. BUG=b:236328487 TEST=Glitching screen was fixed after applying this patch Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Signed-off-by: Hsiao Chien Sung <shawn.sung(a)mediatek.com> Signed-off-by: Jason Chen <Jason-ch.Chen(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8188/pll.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Hsiao Chien Sung: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index 176b884..d892e1c 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -256,7 +256,7 @@ { .id = TOP_SCP_SEL, .sel = 5 }, /* 5: mainpll_d4_d2 */ { .id = TOP_BUS_AXIMEM_SEL, .sel = 1 }, /* 1: mainpll_d7_d2 */ /* CLK_CFG_1 */ - { .id = TOP_VPP_SEL, .sel = 8 }, /* 8: univpll_d6 */ + { .id = TOP_VPP_SEL, .sel = 11 }, /* 11: tvdpll1_ck */ { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */ { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ { .id = TOP_CAM_SEL, .sel = 9 }, /* 9: mainpll_d4_d2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Gerrit-Change-Number: 75661 Gerrit-PatchSet: 3 Gerrit-Owner: jason-ch chen <Jason-ch.Chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hsiao Chien Sung <shawn.sung(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74363?usp=email ) Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 ...................................................................... mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 Define a CMOS layout for Librem Mini v1/v2 spanning both banks. The only setting provided is the automatic power-on setting, which is implemented by the EC. This can now be configured in a firmware image by replacing cmos.default in CBFS. Since cmos.default is applied early in bootblock, the EC BRAM interface must now be configured in bootblock, including opening the LPC I/O range. Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74363 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/purism/librem_cnl/Kconfig M src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c A src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default A src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout 5 files changed, 64 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 0c17ec9..ef05a3e 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -15,11 +15,15 @@ config BOARD_PURISM_LIBREM_MINI select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE select SOC_INTEL_WHISKEYLAKE select SUPERIO_ITE_IT8528E config BOARD_PURISM_LIBREM_MINI_V2 select BOARD_PURISM_BASEBOARD_LIBREM_CNL + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE select SOC_INTEL_COMETLAKE_1 select SUPERIO_ITE_IT8528E @@ -85,6 +89,12 @@ config PC_CMOS_BASE_PORT_BANK1 default 0x360 +config CMOS_LAYOUT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/variants/librem_mini/cmos.layout" + +config CMOS_DEFAULT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/variants/librem_mini/cmos.default" + endif config ENABLE_EC_UART1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc index 20ff438..874cde1 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc @@ -2,3 +2,4 @@ all-y += die.c smm-y += die.c +bootblock-y += bootblock.c diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c new file mode 100644 index 0000000..558815c --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/bootblock.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8528e/it8528e.h> +#include <intelblocks/lpc_lib.h> + +void bootblock_mainboard_early_init(void) +{ + /* + * Enable the EC BRAM interface, and set bank 1's I/O BAR. + * BRAM on this board uses bank 0 from the PCH and bank 1 from the EC: + * + * - PCH bank 0 is used for the RTC. Either should work, but the PCH + * RTC was used historically, and it's preferable not to change this + * in an update. + * - EC bank 1 contains the automatic-power-on setting, which is useful + * to use the Mini as an appliance-like server. + * + * cmos.default can be used to configure the automatic power-on setting + * in firmware. We have to set up the BRAM interface in bootblock, + * because cmos.default is applied early in bootblock. + */ + const pnp_devfn_t ec_rtct_dev = PNP_DEV(0x2E, IT8528E_RTCT); + pnp_enter_conf_state(ec_rtct_dev); + pnp_set_logical_device(ec_rtct_dev); + pnp_set_enable(ec_rtct_dev, 1); + pnp_set_iobase(ec_rtct_dev, 0x62, CONFIG_PC_CMOS_BASE_PORT_BANK1); + pnp_exit_conf_state(ec_rtct_dev); + + /* Open the BRAM 1 bank interface on LPC */ + lpc_open_pmio_window(CONFIG_PC_CMOS_BASE_PORT_BANK1, 2); +} diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default new file mode 100644 index 0000000..1c414b3 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.default @@ -0,0 +1 @@ +power_on_after_fail=Disable diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout new file mode 100644 index 0000000..454ea8b --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +entries + +# start-bit length config config-ID name +0 112 r 0 reserved_memory +1352 8 e 1 power_on_after_fail + +enumerations +#ID value text +1 0 Enable +1 1 Disable + +checksums + +# The EC firmware does initialize power_on_after_fail if it is invalid, but it +# does not have a checksum. Put a checksum at the end of bank 1. +checksum 1352 1359 1520 -- To view, visit https://review.coreboot.org/c/coreboot/+/74363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 11 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/mediatek/common: Disable DRAM scramble by default
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75562?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common: Disable DRAM scramble by default ...................................................................... soc/mediatek/common: Disable DRAM scramble by default Geralt SoC does not support 'persist certain regions' across reboots. Considering the impact of missing ramoops for debugging, set MEDIATEK_DRAM_SCRAMBLE to default n to disable this feature in production FW image. BUG=b:269049451,b:278478563 TEST=emerge-geralt coreboot and confirm CONFIG_MEDIATEK_DRAM_SCRAMBLE=n Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/75562 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Hung-Te Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 1ca0b98..d44b4d1 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -32,7 +32,7 @@ config MEDIATEK_DRAM_SCRAMBLE bool - default y + default n help This option enables DRAM data scramble, which can prevent DRAM data from being hacked. -- To view, visit https://review.coreboot.org/c/coreboot/+/75562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109634d811a928e3e6f7f56e706a5b61a52a21ab Gerrit-Change-Number: 75562 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/mediatek/mt8195: Fix typo for SPIM2_MI
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75726?usp=email ) Change subject: soc/mediatek/mt8195: Fix typo for SPIM2_MI ...................................................................... soc/mediatek/mt8195: Fix typo for SPIM2_MI Fix a typo in an enum type name, "PIM2_MI" -> "SPIM2_MI". TEST=emerge-cherry coreboot Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75726 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8195/include/soc/gpio.h M src/soc/mediatek/mt8195/spi.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Hung-Te Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8195/include/soc/gpio.h b/src/soc/mediatek/mt8195/include/soc/gpio.h index 08fb64b..60f3af1 100644 --- a/src/soc/mediatek/mt8195/include/soc/gpio.h +++ b/src/soc/mediatek/mt8195/include/soc/gpio.h @@ -467,7 +467,7 @@ SPIM2_MO, SPINOR_IO0, SNFI_MOSI, DMIC4_DAT, RES5, RES6, DBG_MON_A12), PIN(143, SPIM2_MI, 0, 19, 0x21, 0xb0, - PIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK, + SPIM2_MI, SPINOR_IO1, SNFI_MISO, DMIC4_CLK, RES5, RES6, DBG_MON_A13), }; diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c index 2772612..98b0d54 100644 --- a/src/soc/mediatek/mt8195/spi.c +++ b/src/soc/mediatek/mt8195/spi.c @@ -56,7 +56,7 @@ PAD_FUNC(SPIM1_CLK, SPIM1_CLK), }, { - PAD_FUNC(SPIM2_MI, PIM2_MI), + PAD_FUNC(SPIM2_MI, SPIM2_MI), PAD_FUNC_GPIO(SPIM2_CSB), PAD_FUNC(SPIM2_MO, SPIM2_MO), PAD_FUNC(SPIM2_CLK, SPIM2_CLK), -- To view, visit https://review.coreboot.org/c/coreboot/+/75726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43a044dc69a93ad1dcaa5e65c66a82046a40777 Gerrit-Change-Number: 75726 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: acpi/acpi.c: Reduce scope of functions used locally
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75732?usp=email ) Change subject: acpi/acpi.c: Reduce scope of functions used locally ...................................................................... acpi/acpi.c: Reduce scope of functions used locally Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75732 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 5 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 4fdbd6f..6ee5cf4 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -110,7 +110,7 @@ i + 1, entries_num, rsdt->header.length); } -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, +static int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); @@ -197,7 +197,7 @@ return current; } -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, +static int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base) { ioapic->type = IO_APIC; /* I/O APIC structure */ @@ -244,7 +244,7 @@ #endif } -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, +static int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ @@ -257,7 +257,7 @@ return irqoverride->length; } -int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride) +static int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride) { u8 gsi, irq, flags; @@ -331,7 +331,7 @@ return current; } -unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) +static unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current) { current = acpi_create_madt_lapics(current); current = acpi_create_madt_lapic_nmis(current); diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 548b4c3..c981ee1 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1363,15 +1363,9 @@ int acpi_create_cedt_cfmws(acpi_cedt_cfmws_t *cfmws, u64 base_hpa, u64 window_size, u8 eniw, u32 hbig, u16 restriction, u16 qtg_id, const u32 *interleave_target); -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base); int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr); -int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags); -int acpi_create_madt_sci_override(acpi_madt_irqoverride_t *irqoverride); unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 cpu, u32 apic); -unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current); unsigned long acpi_create_madt_lapic_nmis(unsigned long current); @@ -1385,8 +1379,6 @@ */ int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain, u16 seg, u8 bus, u8 dev, u8 func, u32 flags); -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, - u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)); -- To view, visit https://review.coreboot.org/c/coreboot/+/75732?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca5d8d175923f690ebfa3108e393e029ea97c80 Gerrit-Change-Number: 75732 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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