coreboot-gerrit June 2023

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: Enable touchscreen
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75692?usp=email ) Change subject: mb/google/rex/var/screebo: Enable touchscreen ...................................................................... mb/google/rex/var/screebo: Enable touchscreen Enable ILI2901 and eKTH7B18 touchscreen for Google Screebo. BUG=b:278167967 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchscreen works. Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Signed-off-by: Zhongtian Wu <wuzhongtian(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75692 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved Rui Zhou: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index d66d7bd..8669d95 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -13,6 +13,11 @@ option MB_TYPEC 1 option MB_TBT 2 end + field TOUCHSCREEN 8 9 + option TOUCHSCREEN_UNKNOWN 0 + option TOUCHSCREEN_ILITEK 1 + option TOUCHSCREEN_ELAN 2 + end end chip soc/intel/meteorlake @@ -368,6 +373,43 @@ end end end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ILTK0001"" + register "generic.desc" = ""ILITEK Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C01)" + register "generic.reset_delay_ms" = "200" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C06)" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 41 on + probe TOUCHSCREEN TOUCHSCREEN_ILITEK + end + end + chip drivers/i2c/hid + register "generic.hid" = ""EKTH7B18U"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C07_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C01)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C00)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C06)" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TOUCHSCREEN TOUCHSCREEN_ELAN + end + end + end device ref i2c3 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/75692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Gerrit-Change-Number: 75692 Gerrit-PatchSet: 6 Gerrit-Owner: zhongtian wu <wuzhongtian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/smm: Sanity check the SMM TSEG size
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75405?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/smm: Sanity check the SMM TSEG size ...................................................................... soc/amd/smm: Sanity check the SMM TSEG size As per AMD64 Architecture Programmer's Manual, section 10.2.5 SMRAM Protected Areas: The TSEG range must be aligned to a 128 Kbyte boundary and the minimum TSEG size is 128 Kbytes. The SMM TSEG size should be less than SMM reserved size. AMD TSEG mask works like an MTRR. It needs to be aligned to it's size and it's size needs to be a power of 2. Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75405 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/amd/common/block/include/amdblocks/smm.h 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Himanshu Sahdev: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/amd/common/block/include/amdblocks/smm.h b/src/soc/amd/common/block/include/amdblocks/smm.h index fb2e488..97b11be 100644 --- a/src/soc/amd/common/block/include/amdblocks/smm.h +++ b/src/soc/amd/common/block/include/amdblocks/smm.h @@ -15,4 +15,16 @@ /* See SMITYPE_* for list possible of events. GEVENTS are handled with mainboard_smi_gpi. */ void mainboard_handle_smi(int event); +#if CONFIG_SMM_TSEG_SIZE != 0 +#if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE) +# error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE" +#endif +#if (CONFIG_SMM_TSEG_SIZE < 0x20000) +# error "CONFIG_SMM_TSEG_SIZE must at least be 128KiB" +#endif +#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) +# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#endif +#endif + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Add CPU power limit values
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75730?usp=email ) Change subject: mb/intel/mtlrvp: Add CPU power limit values ...................................................................... mb/intel/mtlrvp: Add CPU power limit values Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for mtlrvp baseboard. BRANCH=None BUG=None TEST=Built the changes Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/mainboard.c M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c 5 files changed, 40 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index ea6c6cb..4f4526e 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -17,6 +17,7 @@ select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_METEORLAKE_U_P diff --git a/src/mainboard/intel/mtlrvp/mainboard.c b/src/mainboard/intel/mtlrvp/mainboard.c index 9621294..2e515f7 100644 --- a/src/mainboard/intel/mtlrvp/mainboard.c +++ b/src/mainboard/intel/mtlrvp/mainboard.c @@ -35,6 +35,13 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h index f755ff0..726a617 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,4 +20,7 @@ /* Function to initialize memory params based on variant */ const struct mb_cfg *variant_memory_params(void); +/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc index cc5cdc1..dafb64b 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc @@ -2,3 +2,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c new file mode 100644 index 0000000..aee3d88 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ +const struct cpu_tdp_power_limits limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 57000, + .pl2_max_power = 57000, + .pl4_power = 114000 + }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_cpu_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75730?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Gerrit-Change-Number: 75730 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/brya/var/hades: Abort power on if any rails fail to come up
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75534?usp=email ) Change subject: mb/google/brya/var/hades: Abort power on if any rails fail to come up ...................................................................... mb/google/brya/var/hades: Abort power on if any rails fail to come up Currently if a rails PG fails to assert, the power on sequence continue after the 20ms timeout. Instead, we should abort and enter a power down. BUG=b:285980464 TEST=sequence now aborts and powers down on failure Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75534 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/hades/variant.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/hades/variant.c b/src/mainboard/google/brya/variants/hades/variant.c index 5cdfabb..0864ec0 100644 --- a/src/mainboard/google/brya/variants/hades/variant.c +++ b/src/mainboard/google/brya/variants/hades/variant.c @@ -83,7 +83,7 @@ pwr_en_state = !pwr_en_state; gpio_output(seq->pwr_en_gpio, pwr_en_state); - result = wait_us(DEFAULT_PG_TIMEOUT_US, gpio_get(seq->pg_gpio) == state) >= 0; + result = wait_us(DEFAULT_PG_TIMEOUT_US, gpio_get(seq->pg_gpio) == state) > 0; if (seq->delay_ms) mdelay(seq->delay_ms); -- To view, visit https://review.coreboot.org/c/coreboot/+/75534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Gerrit-Change-Number: 75534 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/docker: Add Alpine Dockerfile
by Felix Singer (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Jan Samek. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75049?usp=email ) Change subject: util/docker: Add Alpine Dockerfile ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/75049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If90412146acc94f01a89cd681539aad48e92dd2e Gerrit-Change-Number: 75049 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 15:21:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits
by Fred Reitberger (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier, Raul Rangel. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75766?usp=email ) Change subject: soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Gerrit-Change-Number: 75766 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 15:13:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits
by Felix Held (Code Review) 12 Jun '23

12 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75766?usp=email ) Change subject: soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits ...................................................................... soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits Rename get_smee_reserved_address_bits to get_sme_reserved_address_bits since the feature is called secure memory encryption and the last 'e' in SMEE bit in the SYSCFG MSR just stands for enable. The function will return a valid number of reserved address bits no matter if this is enabled or not, so drop the second 'e'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 --- M src/soc/amd/common/block/cpu/noncar/cpu.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/75766/1 diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 891dece..eec593c 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -35,7 +35,7 @@ wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } -static uint32_t get_smee_reserved_address_bits(void) +static uint32_t get_sme_reserved_address_bits(void) { if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE) return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & @@ -47,5 +47,5 @@ uint32_t get_usable_physical_address_bits(void) { - return cpu_phys_address_size() - get_smee_reserved_address_bits(); + return cpu_phys_address_size() - get_sme_reserved_address_bits(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Gerrit-Change-Number: 75766 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: soc/intel/meteorlake: Add support for crashlog
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Kane Chen, Kapil Porwal, Paul Menzel, Pratikkumar V Prajapati, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74769?usp=email ) Change subject: soc/intel/meteorlake: Add support for crashlog ...................................................................... Patch Set 23: (1 comment) File src/soc/intel/meteorlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/74769/comment/3d054363_72c3dda6 : PS23, Line 14: static bool m_pmc_crashLog_support; > Better create a struct for support,present,size ;) i agree this is too long list and there are many optimization required but I guess the agreement is to do that after enabling the feature. -- To view, visit https://review.coreboot.org/c/coreboot/+/74769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0abd697fba35edf1c03d2a3a325b7785b985cd5 Gerrit-Change-Number: 74769 Gerrit-PatchSet: 23 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 14:33:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75625?usp=email ) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > This is common code change, shouldn't we keep this patch separate from MTL specific patch? hmm, make sense. then you need to highlight that follow by SoC specific cl will make use of common code kconfig -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 14:32:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: lib/coreboot_table.c: Add a pointer to SMBIOS in coreboot tables
by Benjamin Doron (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, David Milosevic, Maximilian Brune. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75765?usp=email ) Change subject: lib/coreboot_table.c: Add a pointer to SMBIOS in coreboot tables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796dd426feefb0785c0222fb4fc34dae7b70982c Gerrit-Change-Number: 75765 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 14:27:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2023