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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/35e13d07_a126b103 :
PS2, Line 207: CLK_REQ3_L
> Do we want a S5 SMI call back to assert the all the RST?
Not required. When the system enters S5, all these GPIOs automatically get reset and our boot flow gives sufficient time/delay before we reinitialize them in romstage and hit PCIe link training.
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/c747684c_1ba4a8b7 :
PS2, Line 207: CLK_REQ3_L
> I think we did not do it in Skyrim since all the concerned GPIOs, at least the AUX_RST_L GPIOs, were […]
Do we want a S5 SMI call back to assert the all the RST?
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Change subject: mb/google/myst: Update PCIe romstage gpios
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Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/cf26f805_17ca968b :
PS2, Line 207: CLK_REQ3_L
> The SSD clock request line is required before PCIe link training. […]
I think we did not do it in Skyrim since all the concerned GPIOs, at least the AUX_RST_L GPIOs, were in S0 domain. On Myst, all the AUX_RST_L GPIOs are in S5 domain. Since we are hearing different things about warm reset, I will recommend to initialize AUX_RST_L and CLK_REQ_L lines for all WLAN, SD and SSD PCIe GPP ports before PCIe link training. If you want to do that as a follow-up CL, I am fine. But strongly recommend to do that in preparation for warm reset. Otherwise when warm reset is enabled in SoC code, we may be observing failures/regressions.
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 6:
(1 comment)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/75756/comment/da3a53ff_61266bd9 :
PS5, Line 362: config DUMP_SMBIOS_TYPE17
: bool
: default n
: help
: Dump part of SMBIOS type17 dimm information
> IMHO, we already have SPD dump print, information are duplicated. This is useful for DDR5 for now. […]
Acknowledged
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
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Patch Set 6:
(1 comment)
Patchset:
PS6:
I am planing to clean and add the max_speed from memory_hob. Which I found ADLN only support 4800MT and we use the 5200. Also RPL only up to 5200MT and we use 5600. Print it is helpful and you can't see it from SPD. After clean up, I'll set the to visible ;p
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Hello Eric Lai, Kapil Porwal, Subrata Banik, Sumeet R Pawnikar, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+2 by Subrata Banik
Change subject: mb/google/rex/variants/ovis: Add basic DTT
......................................................................
mb/google/rex/variants/ovis: Add basic DTT
Add default Intel DPTF.
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
---
M src/mainboard/google/rex/variants/ovis/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75580/8
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Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75700/comment/28e34365_b85bf93f :
PS4, Line 55: PAD_NFO(GPIO_27, PCIE_RST1_L, LOW),
> PCIE_RST1_L isn't connected to anything, so there's no point in driving it high. […]
Acknowledged
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Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75700/comment/41485173_b587d3e5 :
PS4, Line 55: PAD_NFO(GPIO_27, PCIE_RST1_L, LOW),
> sorry, I am little confused here. […]
PCIE_RST1_L isn't connected to anything, so there's no point in driving it high. This is just cleanup
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