coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Fix memory max capacity per processor
by Ziang Wang (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Hello Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75740?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Lean Sheng Tan, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/spr: Fix memory max capacity per processor ...................................................................... soc/intel/xeon_sp/spr: Fix memory max capacity per processor The capacity shall be 6*TiB per processor. Tested on SPR-SP EagleStream Platform, this patch corrects the mem capacity shown in SMBIOS type17. Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Signed-off-by: Hao Wang <wanghao11(a)inspur.com> Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/soc/intel/xeon_sp/spr/romstage.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 6 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Fix HEST table length
by Lean Sheng Tan (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Paul Menzel, TangYiwei, Tim Chu, Ziang Wang. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75738?usp=email ) Change subject: soc/intel/xeon_sp: Fix HEST table length ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Gerrit-Change-Number: 75738 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:21:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: Add SPR_MEM_CAPACITY macro
by Ziang Wang (Code Review) 12 Jun '23

12 Jun '23

Ziang Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75759?usp=email ) Change subject: Add SPR_MEM_CAPACITY macro ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idabcafa29f18dac5c0d50a2fca0bcd19f441d34c Gerrit-Change-Number: 75759 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: elog: Add PSR backup eventlog messages
by Krishna P Bhat D (Code Review) 12 Jun '23

12 Jun '23

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75760?usp=email ) Change subject: elog: Add PSR backup eventlog messages ...................................................................... elog: Add PSR backup eventlog messages Change-Id: I2459a2b941d28a87b6c78f75dbe8779d73328d7a Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/75760/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index 783557f..9ab5232 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -372,6 +372,13 @@ /* Only the 7-LSB are used for size */ #define ELOG_MAX_EVENT_SIZE 0x7F +/* PSR Events */ +#define ELOG_TYPE_PSR_DATA_BACKUP 0xb9 +#define ELOG_PSR_DATA_BACKUP_SUCCESS 0 +#define ELOG_PSR_DATA_BACKUP_FAILED 1 + +#define ELOG_PSR_DATA_LOST 0xba + enum cb_err elog_verify_header(const struct elog_header *header); const struct event_header *elog_get_next_event(const struct event_header *event); const void *event_get_data(const struct event_header *event); diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index eff5bb7..1088acf 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -6,6 +6,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <cpu/cpu.h> +#include <elog.h> #include <fmap.h> #include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> @@ -786,11 +787,18 @@ if (heci_send_receive(&req, sizeof(req), &backup_psr_resp, &resp_size, HECI_PSR_ADDR)) { printk(BIOS_ERR, "cse_lite: could not backup PSR data\n"); + elog_add_event_byte(ELOG_TYPE_PSR_DATA_BACKUP, ELOG_PSR_DATA_BACKUP_FAILED); } else { printk(BIOS_DEBUG, "cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent\n"); - if (backup_psr_resp.status != PSR_STATUS_SUCCESS) + if (backup_psr_resp.status != PSR_STATUS_SUCCESS) { printk(BIOS_DEBUG, "cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command" "returned %d\n", (int)backup_psr_resp.status); + elog_add_event_byte(ELOG_TYPE_PSR_DATA_BACKUP, + ELOG_PSR_DATA_BACKUP_FAILED); + } else { + elog_add_event_byte(ELOG_TYPE_PSR_DATA_BACKUP, + ELOG_PSR_DATA_BACKUP_SUCCESS); + } } /* We have sent PSR backup command. Update this info in CMOS */ @@ -806,6 +814,8 @@ if (status == CSE_UPDATE_DOWNGRADE) backup_psr_data(cse_bp_info); + if (status == CSE_UPDATE_CORRUPTED) + elog_add_event(ELOG_PSR_DATA_LOST); /* * To set CSE's operation mode to HMRFPO mode: * 1. Ensure CSE to boot from RO(BP1) -- To view, visit https://review.coreboot.org/c/coreboot/+/75760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2459a2b941d28a87b6c78f75dbe8779d73328d7a Gerrit-Change-Number: 75760 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: Add SPR_MEM_CAPACITY macro
by Ziang Wang (Code Review) 12 Jun '23

12 Jun '23

Ziang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75759?usp=email ) Change subject: Add SPR_MEM_CAPACITY macro ...................................................................... Add SPR_MEM_CAPACITY macro Change-Id: Idabcafa29f18dac5c0d50a2fca0bcd19f441d34c Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/soc/intel/xeon_sp/spr/romstage.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/75759/1 diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 62b6212..96499fc 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -22,6 +22,10 @@ #include "chip.h" +#ifndef SPR_MEM_CAPACITY_IN_MB +#define SPR_MEM_CAPACITY_IN_MB (6 * (1 << 20)) +#endif + /* Initialize to all zero first */ static UPD_IIO_PCIE_PORT_CONFIG spr_iio_bifur_table[MAX_SOCKET]; static UINT8 deemphasis_list[MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET]; @@ -276,7 +280,7 @@ * Max Capacity: (x8 256 GB 16 Gb 3DS DDR5) and (x8 512 GB Intel® Optane™ * Persistent Memory 300 Series mapped as memory) per Socket */ - mem_info->max_capacity_mib = 6 * MiB * CONFIG_MAX_SOCKET; + mem_info->max_capacity_mib = SPR_MEM_CAPACITY_IN_MB * CONFIG_MAX_SOCKET; mem_info->number_of_devices = CONFIG_DIMM_MAX; mem_info->ecc_type = get_error_correction_type(hob->RasModesEnabled); dimm_max = ARRAY_SIZE(mem_info->dimm); -- To view, visit https://review.coreboot.org/c/coreboot/+/75759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idabcafa29f18dac5c0d50a2fca0bcd19f441d34c Gerrit-Change-Number: 75759 Gerrit-PatchSet: 1 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Singer, Kapil Porwal, Meera Ravindranath, Paul Menzel, Ronak Kanabar, Sridhar Siricilla, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 4: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/75663/comment/452a18a0_1dbf6803 : PS4, Line 208: #error You need to implement this struct for x86_64 FSP : #endif : > This is not required any more as FSPM_ARCH2_UPD/ FSPS_ARCH2_UPD/FSPT_ARCH2_UPD declaration reflects support for 64 bit FSP (PLATFORM_USES_FSP2_X86_64) as well. can u please point those structure definition for X86_64? -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 10:05:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/joxer: Add DmaProperty for ISH
by Mark Hsieh (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Held, Henry Sun, Reka Norman, Sam McNally, Shou-Chieh Hsu. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75758?usp=email ) Change subject: mb/google/nissa/var/joxer: Add DmaProperty for ISH ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/75758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f Gerrit-Change-Number: 75758 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 12 Jun 2023 09:54:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Sridhar Siricilla (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Felix Singer, Kapil Porwal, Meera Ravindranath, Paul Menzel, Ronak Kanabar, Tarun Tuli. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 4: (2 comments) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/75663/comment/1ec39087_c363b85f : PS4, Line 207: #else #endif https://review.coreboot.org/c/coreboot/+/75663/comment/3b7e34e9_fe697dff : PS4, Line 208: #error You need to implement this struct for x86_64 FSP : #endif : This is not required any more as FSPM_ARCH2_UPD/ FSPS_ARCH2_UPD/FSPT_ARCH2_UPD declaration reflects support for 64 bit FSP (PLATFORM_USES_FSP2_X86_64) as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 09:47:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Fix HEST table length
by Ziang Wang (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Nico Huber, Paul Menzel, TangYiwei, Tim Chu. Ziang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75738?usp=email ) Change subject: soc/intel/xeon_sp: Fix HEST table length ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Sorry, that's the 'Undefined Behavior Sanitizer'. It's something you can compile […] Gotcha, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/75738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Gerrit-Change-Number: 75738 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 09:44:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Ziang Wang <ziang.wang(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Subrata Banik (Code Review) 12 Jun '23

12 Jun '23

Attention is currently required from: Eric Lai, Paul Menzel, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 5: (2 comments) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/0dfb6ea2_06116e2b : PS5, Line 263: if (code >= 0x01 && code <= 0x23) : return type[code - 0x01]; : return "Unsupported memory type"; WDYT? ``` if (!(code >= 0x01 && code <= 0x23)) return "Unsupported memory type"; return type[code - 0x01]; ``` https://review.coreboot.org/c/coreboot/+/75756/comment/2cad3203_38c81ebb : PS5, Line 1046: i would have called below func from here ``` if (CONFIG(DUMP_SMBIOS_TYPE17)) dump_smbios_type17(dimm); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 12 Jun 2023 09:27:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023