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Change subject: soc/intel/cmd/blk/cse: Add a kconfig option to store CSE version
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/75746/comment/b87656ea_b5185782 :
PS1, Line 48: SOC_INTEL_STORE_CSE_VERSION
> nit:Feedback from community to use cache instead store...may be SOC_INTEL_CACHE_CSE_RW_FW_VERSION?
i don't think Cache is the right terminology here because the source of the cache is always assumed as temp memory but here the goal is to store inside persistent memory.
I won't ignore this Kconfig as we don't need this.
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Change subject: vendorcode/intel: Add edk2-stable202302 support
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h:
https://review.coreboot.org/c/coreboot/+/75663/comment/de5c80bb_b366d956 :
PS4, Line 208: #error You need to implement this struct for x86_64 FSP
: #endif
:
> For now, can we remove the "#else" part? Agreed?
I guess the else part if not needed now.
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 9:
(2 comments)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/75756/comment/0899b64f_6773a25a :
PS5, Line 362: config DUMP_SMBIOS_TYPE17
: bool
: default n
: help
: Dump part of SMBIOS type17 dimm information
> Acknowledged
do we need choice ?
can't we have something similar ?
```
config DUMP_SMBIOS_TYPE17
bool "Dump part of SMBIOS type17 dimm information."
default n
help
Dump part of SMBIOS type17 dimm information.
```
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/75756/comment/252884d5_18e99444 :
PS9, Line 265: 0x1A
do we have any existing macro for DDR4 (somewhere in the code)?
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Change subject: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
Why not override the information in CBMEM_ID_MEMINFO instead before smbios is created?
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Change subject: soc/intel: Add max memory speed into dimm info
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75810/comment/d369a4e6_c431ee0f :
PS4, Line 31: Configured Memory Speed: 5200 MT/s
is this the newer entry ?
Patchset:
PS4:
is
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Hello Angel Pons, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Nico Huber, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75729?usp=email
to look at the new patch set (#3).
Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
......................................................................
UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HId device needs to reserve this region.
Instead of having this code in each DSDT, add this via SSDT on all
platforms with CONFIG_ECAM_MMCONF_SUPPORT.
As no AMD platforms has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table so that Linux in such a way that it prevents Linux from using PCIe
ECAM. This change fixes that problem.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
---
M src/acpi/acpi.c
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/soc/intel/apollolake/acpi/northbridge.asl
M src/soc/intel/baytrail/acpi/southcluster.asl
M src/soc/intel/braswell/acpi/southcluster.asl
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/denverton_ns/acpi/northcluster.asl
M src/soc/intel/skylake/acpi/systemagent.asl
14 files changed, 38 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75729/3
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Change subject: util/docker: Add Alpine Dockerfile
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> I am using Alpine on a native machine and I wanted to have a functional coreboot build. […]
Cool. Well my intention wasn't to have everything working with this patch. I rather intended to provide a common base in order to collaborate on improving the musl support. Alpine seems to be one of the most popular distros using musl as libc. So I decided to use that for this purpose and for my CI replacement.
Also, I rather would like to find out the root cause for the issue and try to fix that before we start using a workaround. I mean, obviously it should work for both ways.
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Change subject: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
you can tweak your SPD or dimm info.
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Change subject: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > Serial should read by SPD, why do you want to overwrite it? […]
Explaining the situation here on behalf of @tangyiwei.2022@bytedance.com: Bytedance is using a (self-defined) aggregated DIMM serial message, I guess they are used by other platform management protocols.
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Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75049?usp=email )
Change subject: util/docker: Add Alpine Dockerfile
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Awesome! Thank you. I didn't have the time to take a closer look yet. […]
I am using Alpine on a native machine and I wanted to have a functional coreboot build. I now have with this workarnound, and I think building the tools statically shouldn't harm at all.
I can give this +1 when this workaround is used, as I would prefer an unbiased +2 :) .
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