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Change subject: util/docker: Add Alpine Dockerfile
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Cool. Well my intention wasn't to have everything working with this patch. […]
OK, that makes fully sense and I would also like to see a coreboot build running on Alpine out-of-the-box (because it used to be out-of-the-box not so long ago).
Do you think it made sense to provide the steps with building cbfstool and the subsequent segfault and additional findings to the Alpine bug tracker?
I think Alpine already provides an outstanding support for building and supporting coreboot in runtime also on non-x86 architectures (including libgfxinit!) and would be a pity, when this capability would be ruined by this little annoying bug.
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Change subject: mb/google/rex: change ramstage compression to LZ4
......................................................................
Patch Set 4:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75769/comment/1c1758a1_ee4832f2 :
PS4, Line 7: change ramstage compression to LZ4
Maybe:
> LZ4 compress ramstage instead of LZMA
https://review.coreboot.org/c/coreboot/+/75769/comment/adc94b7a_71a48b24 :
PS4, Line 10: 35ms(30-37ms)
Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/75769/comment/c642771d_640741a8 :
PS4, Line 24:
Thank you adding the data. Could you please also mention the flash ROM chip, that was used.
https://review.coreboot.org/c/coreboot/+/75769/comment/d773ee46_76db7452 :
PS4, Line 25: (
Please put the space before the (.
https://review.coreboot.org/c/coreboot/+/75769/comment/8672b384_4d8059d5 :
PS4, Line 27: 165452
Is that the right value?
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Change subject: mb/google/nissa/yaviks: Tuning eMMC DLL value for eMMC initialization error
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75812/comment/b2032a92_938229b4 :
PS1, Line 7: Tuning
Please use imperative mood: Tune …
https://review.coreboot.org/c/coreboot/+/75812/comment/cb2046e3_c5c8166e :
PS1, Line 9:
Please describe the problem/error.
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Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation
......................................................................
Patch Set 3: -Code-Review
(2 comments)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/75625/comment/3043aad7_b7770f91 :
PS3, Line 145: INTEL_TME_GEN_NEW_KEY_EACH_WARM_REBOOT
INTEL_TME_UPDATE_KEY_ON_WARM_BOOT or INTEL_TME_GENERATE_KEY_ON_WARM_BOOT
https://review.coreboot.org/c/coreboot/+/75625/comment/23f7d938_1df7eee4 :
PS3, Line 155: INTEL_TME_EXCLUDE_CBMEM
how about the below name knowing this is file for intel common code hence, dropping the intel here.
`TME_EXCLUDE_CBMEM_PROTECTION`
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Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation
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Patch Set 3: Code-Review+2
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Change subject: common/block/cse: Add config to split CSE firmware sync
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
overall we need to agree on a few things
1. traditionally, CSE sync is the way to perform two operations
a. switch from CSE RO to CSE RW
b. Allow CSE fw upgrade or downgrade if required
with the modified proposal, we are keeping the 1a. early in romstage (which we can't call it anymore CSE sync).
1b. is flexible either romstage or ramstage. maybe for PSR enabled platform, it will be in ramstage. the RPL-R or ADL devices, it still is performing the 1b. inside romstage.
hence, i would suggest to have three config to clarify the job description and call out the dependency in proper.
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 9:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/75756/comment/60fdc679_7017af21 :
PS9, Line 226: /* skip old type for save static memory
: "Other",
: "Unknown",
: "DRAM",
: "EDRAM",
: "VRAM",
: "SRAM",
: "RAM",
: "ROM",
: "Flash",
: "EEPROM",
: "FEPROM",
: "EPROM",
: "CDRAM",
: "3DRAM",
: "SDRAM",
: "SGRAM",
: "RDRAM",
: "DDR",
: "DDR2",
: "DDR2 FB-DIMM",
: "Reserved",
: "Reserved",
: "Reserved",
: "DDR3",
: "FBD2",
: */
> Is printing SMBIOS information for older DRAM specs not desirable? It will print unsupported type, which is incorrect.
+2
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 9:
(2 comments)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/75756/comment/e81c0681_4eea0069 :
PS9, Line 362: choice
: prompt "Dump SMBIOS type17"
: default n
: depends on GENERATE_SMBIOS_TABLES
drop the choice.
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/75756/comment/86d64af5_8dbcc560 :
PS9, Line 226: /* skip old type for save static memory
: "Other",
: "Unknown",
: "DRAM",
: "EDRAM",
: "VRAM",
: "SRAM",
: "RAM",
: "ROM",
: "Flash",
: "EEPROM",
: "FEPROM",
: "EPROM",
: "CDRAM",
: "3DRAM",
: "SDRAM",
: "SGRAM",
: "RDRAM",
: "DDR",
: "DDR2",
: "DDR2 FB-DIMM",
: "Reserved",
: "Reserved",
: "Reserved",
: "DDR3",
: "FBD2",
: */
Is printing SMBIOS information for older DRAM specs not desirable? It will print unsupported type, which is incorrect.
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