coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Ziang Wang (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Hello Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75740?usp=email to look at the new patch set (#9). Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... soc/intel/xeon_sp/spr: Add weak method to get memory capability Memory capacity could be 4TB or 6TB on different SPR SKUs, instead of setting it statically at SoC level, it is better using a weak function that can be overrode by mainboard. Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/soc/intel/xeon_sp/spr/romstage.c 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 9 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/spr/romstage.c: https://review.coreboot.org/c/coreboot/+/75740/comment/9171f5d4_9f290d45 : PS8, Line 45: without with? -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 8 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 07:36:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Ziang Wang (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Hello Arthur Heymans, Christian Walter, Eric Lai, Felix Singer, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75740?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review-1 by Ziang Wang, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... soc/intel/xeon_sp/spr: Add weak method to get memory capability Memory capacity could be 4TB or 6TB on different SPR SKUs, instead of setting it statically at SoC level, it is better using a weak function that can be overrode by mainboard. Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Signed-off-by: Ziang Wang <ziang.wang(a)intel.com> --- M src/soc/intel/xeon_sp/spr/romstage.c 1 file changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 8 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/rex: change ramstage compression to LZ4
by Wonkyu Kim (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Arthur Heymans, Jamie Ryu, Kapil Porwal, Raj Astekar, Subrata Banik, Tarun Tuli. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75769?usp=email ) Change subject: mb/google/rex: change ramstage compression to LZ4 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75769/comment/52edcd7d_ae4d24ae : PS3, Line 13: Exitsing > existing. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 07:27:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: change ramstage compression to LZ4
by Wonkyu Kim (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Jamie Ryu, Kapil Porwal, Raj Astekar, Subrata Banik, Tarun Tuli, Wonkyu Kim. Hello Arthur Heymans, Jamie Ryu, Kapil Porwal, Raj Astekar, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75769?usp=email to look at the new patch set (#4). Change subject: mb/google/rex: change ramstage compression to LZ4 ...................................................................... mb/google/rex: change ramstage compression to LZ4 for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms(30-37ms) while SPI size impact is 230KB. For detail, refer below. Existing: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact( 73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded --- M src/mainboard/google/rex/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/75769/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
by Arthur Heymans (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Angel Pons, Jeff Daly, Lance Zhao, Matt DeVillier, Nico Huber, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75729?usp=email ) Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT ...................................................................... Patch Set 2: (2 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75729/comment/3435b5ea_ffebb96d : PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN); : assert(dev != NULL); > We could also export domain devices to `build/static_devices.h`. > > OTOH, filtering the right device in the loop device should do too. On some upcoming, not yet upstream AMD platform I use domain numbers to match an ID on the data fabric. That would make static_devices.h harder to use. https://review.coreboot.org/c/coreboot/+/75729/comment/456f085a_acfb67c4 : PS2, Line 594: 1 > Shouldn't this be unique (I'm not sure about the scope)? i.e. not the same > as in the static `.asl` files. I tried to find a device name not found in DSDT and just set _UID to 1 without a particular reason (probably copied from existing DSDT) -- To view, visit https://review.coreboot.org/c/coreboot/+/75729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Gerrit-Change-Number: 75729 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 07:17:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/dedede/var/boxy: Update Audio Codec HID for Boxy
by Kevin3 Yang (Code Review) 13 Jun '23

13 Jun '23

Kevin3 Yang has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/75813?usp=email ) Change subject: mb/google/dedede/var/boxy: Update Audio Codec HID for Boxy ...................................................................... mb/google/dedede/var/boxy: Update Audio Codec HID for Boxy Boxy audio codec chip using ALC5682I-VD, not ALC5682I-VS. It need to modify codec HID to "10EC5682" in coreboot to fix audio no output sound issue. BUG=b:286970886 BRANCH=dedede TEST=build and confirm audio can output sound Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Signed-off-by: Kevin Yang <kevin3.yang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75813/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75813?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Gerrit-Change-Number: 75813 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/dedede/var/boxy:Update Audio Codec HID for Boxy
by Kevin3 Yang (Code Review) 13 Jun '23

13 Jun '23

Kevin3 Yang has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/75813?usp=email ) Change subject: mb/google/dedede/var/boxy:Update Audio Codec HID for Boxy ...................................................................... mb/google/dedede/var/boxy:Update Audio Codec HID for Boxy Boxy audio codec chip using ALC5682I-VD, not ALC5682I-VS. It need to modify codec HID to "10EC5682" in coreboot to fix audio no output sound issue. BUG=b:286970886 BRANCH=dedede TEST=build and confirm audio can output sound Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Signed-off-by: Kevin Yang <kevin3.yang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75813/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75813?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Gerrit-Change-Number: 75813 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: modify codec modify codec
by Kevin3 Yang (Code Review) 13 Jun '23

13 Jun '23

Kevin3 Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75813?usp=email ) Change subject: modify codec modify codec ...................................................................... modify codec modify codec Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Signed-off-by: Kevin Yang <kevin3.yang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boxy/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75813/1 diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index 8b51432..0c50acd 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -173,7 +173,7 @@ device pci 15.3 off end # I2C 3 device pci 19.0 on chip drivers/i2c/generic - register "hid" = ""RTL5682"" + register "hid" = ""10EC5682"" register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" -- To view, visit https://review.coreboot.org/c/coreboot/+/75813?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd69a9d757ba817b586a703a17375682db684224 Gerrit-Change-Number: 75813 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util/docker: Add Alpine Dockerfile
by Jan Samek (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Felix Singer, Martin L Roth. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75049?usp=email ) Change subject: util/docker: Add Alpine Dockerfile ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > I found a workaround - set `TOOLLDFLAGS=-static` during the build. […] I even manually compiled musl on other non-alpine machine and linked cbfstool against musl and it worked fine. So this might only be an alpine-specific bug. -- To view, visit https://review.coreboot.org/c/coreboot/+/75049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If90412146acc94f01a89cd681539aad48e92dd2e Gerrit-Change-Number: 75049 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 07:07:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023