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Change subject: util/docker: Add Alpine Dockerfile
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> I even manually compiled musl on other non-alpine machine and linked cbfstool against musl and it wo […]
Awesome! Thank you. I didn't have the time to take a closer look yet. I will try at some later point. Though, could we get this in meanwhile?
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Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
Patch Set 10:
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Patchset:
PS10:
> Just verified, it works, at least under config.intel.crb. […]
Thank you!
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Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> BTW, could you help verify this CL https://review.coreboot.org/c/coreboot/+/75810? Should be work.
Just verified, it works, at least under config.intel.crb.ac
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Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
Patch Set 10: Code-Review+1
(1 comment)
Patchset:
PS10:
BTW, could you help verify this CL https://review.coreboot.org/c/coreboot/+/75810? Should be work.
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Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
mb/google/dedede: Support variant specific power limits
With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
---
M src/mainboard/google/dedede/variants/baseboard/Makefile.inc
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/dedede/variants/baseboard/ramstage.c
3 files changed, 146 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/6
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Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
ops, sorry forgot to also add the header
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Code-Review+1 by Eric Lai
Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
soc/intel/xeon_sp/spr: Add weak method to get memory capability
Memory capacity could be 4TB or 6TB on different SPR SKUs, instead of
setting it statically at SoC level, it is better using a weak function
that can be overrode by mainboard.
Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767
Signed-off-by: Ziang Wang <ziang.wang(a)intel.com>
---
M src/soc/intel/xeon_sp/spr/include/soc/ddr.h
M src/soc/intel/xeon_sp/spr/romstage.c
2 files changed, 17 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/75740/10
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Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
Patch Set 9: Code-Review+1
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Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/xeon_sp/spr/romstage.c:
https://review.coreboot.org/c/coreboot/+/75740/comment/dd7c7586_0d54c084 :
PS8, Line 45: without
> with?
Done
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