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Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
mb/google/myst: Update PCIE_RST_L drive
PCIE_RST_L is attached to a pull down, change the init to NC.
BUG=None
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---
M src/mainboard/google/myst/variants/baseboard/gpio.c
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Change subject: mb/google/myst: Update PCIe romstage gpios
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/5388ab7f_b7ee12e7 :
PS3, Line 199: /* PCIE_RST0_L */
: PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
> i'd move deaserting the main reset line to the end of the table so that it'll be done as the last st […]
Done
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Change subject: [WIP] util/abuild: Add parser for statistics
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[WIP] util/abuild: Add parser for statistics
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS3:
have you checked if the time between the reset being deasserted and the pcie training in fsp to begin is less than 20ms? i wonder if we should move the deasserting of PCIE_RSTx_L into pcie init in FSP to make sure that the timing requirements are always met and only do the aux reset configuration in coreboot. currently discussing this internally in a slightly different context
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/5ea7daea_ff55555f :
PS3, Line 199: /* PCIE_RST0_L */
: PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
i'd move deaserting the main reset line to the end of the table so that it'll be done as the last step
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Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
......................................................................
Patch Set 3:
(2 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/75729/comment/6261b0a4_b381e99f :
PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
: assert(dev != NULL);
> > We could also export domain devices to `build/static_devices.h`. […]
Right. I don't remember exactly what I imagined. Probably that we always
have a `domain 0` and only need ECAM for this one?
Anyway, a different thought: This is probably not the right place to decide
what device we add the resource to. Technically we already have the
`.acpi_fill_ssdt` pointer for this. We could set it to a default implementation
depending on CONFIG_ECAM_MMCONF_SUPPORT. And if a platform has its own
fill_ssdt(), it could still call the default one. WDYT?
https://review.coreboot.org/c/coreboot/+/75729/comment/31294bc5_0750b6fd :
PS2, Line 594: 1
> > Shouldn't this be unique (I'm not sure about the scope)? i.e. not the same […]
It should be unique among "PNP0C02" devices. I don't think we need _UID here.
It's probably better not to have one than a wrong one.
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Change subject: mb/google/rex: change ramstage compression to LZ4
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
@kapil, can u please check if build (release and debug) is good with different USE flag being enabled?
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