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Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75761?usp=email )
Change subject: vc/intel/fsp/fsp20/meteorlake: Add VR config entries
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> we have pushed the FSP Cls as well and will wait until hear back from Intel team
done
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Hello Reka Norman, Ryan Lin, Zhuohao Lee, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
mb/google/dedede/var/dibbi: Update power limits
Add ramstage.c in Makefile.inc and update Dibbi power limit in ramstage.
Also update select in Kconfig.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/variants/dibbi/Makefile.inc
A src/mainboard/google/dedede/variants/dibbi/ramstage.c
3 files changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/8
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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/mediatek: Add prompt for the SCRAMBLE config
......................................................................
soc/mediatek: Add prompt for the SCRAMBLE config
Unexpectedly, fwserial.{project} won't override the Kconfig if the
Kconfig prompt is empty.
CONFIG MEDIATEK_DRAM_SCRAMBLE
bool
After adding the prompt after the previous line "bool", i.e.
bool "Enable DRAM scramble feature"
It works!
BUG=b:285474337
TEST=build pass and check scramble feature is disabled on serial build
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Change-Id: I703ac9aa3ccc4dd9d0fef9949c6b0d49449971a4
---
M src/soc/mediatek/common/Kconfig
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/75815/2
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Xixi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75815?usp=email )
Change subject: soc/mediatek: Add prompt for the SCRAMBLE config
......................................................................
soc/mediatek: Add prompt for the SCRAMBLE config
Unexpectedly, fwserial.{project} won't override the Kconfig if the
Kconfig prompt is empty.
CONFIG MEDIATEK_DRAM_SCRAMBLE
bool
After adding the prompt after the previous line "bool", i.e.
bool "Enable DRAM scramble feature"
It works!
BUG=b:285474337
TEST=build pass and check scramble feature is disabled on serial build
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com>
Change-Id: I703ac9aa3ccc4dd9d0fef9949c6b0d49449971a4
---
M src/soc/mediatek/common/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/75815/1
diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig
index c6a27bc..6ba45c4 100644
--- a/src/soc/mediatek/common/Kconfig
+++ b/src/soc/mediatek/common/Kconfig
@@ -31,7 +31,7 @@
open-source policy.
config MEDIATEK_DRAM_SCRAMBLE
- bool
+ bool "Enable DRAM scramble feature"
default y
help
This option enables DRAM data scramble, which can prevent DRAM data from
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75722/comment/cbb76746_cd943058 :
PS5, Line 19: The board boots to Linux 5.10 with all 192 cores available.
: All PCIe devices 64 and DIMMS are working.
> hi Paul, […]
Done
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Hello Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Patrick Rudolph, Paul Menzel, build bot (Jenkins), niehaitao(a)bytedance.com,
I'd like you to reexamine a change. Please visit
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
mb/bytedance: Add 2 SPR sockets server board bd_egs
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.
It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management
Test:
The board boots to Linux 5.10 with all 192 cores available.
All PCIe devices and DIMMS are working.
Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01(a)ieisystem.com>
Co-authored-by: Long Cao <caolong01(a)inspur.com>
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Co-authored-by: Chenyu Lan <lanchenyu(a)inspur.com>
Co-authored-by: Lay Kong <lay.kong(a)intel.com>
Co-authored-by: Kehong Chen <kehong.chen(a)intel.com>
Co-authored-by: Ziang Wang <ziang.wang(a)intel.com>
Co-authored-by: Dong Wei <weidong.wd(a)bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl(a)bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022(a)bytedance.com>
Reviewed-by: Haitao Nie<niehaitao(a)bytedance.com>
Reviewed-by: Shijian Ge<geshijian(a)bytedance.com>
---
A src/mainboard/bytedance/Kconfig
A src/mainboard/bytedance/Kconfig.name
A src/mainboard/bytedance/bd_egs/Kconfig
A src/mainboard/bytedance/bd_egs/Kconfig.name
A src/mainboard/bytedance/bd_egs/Makefile.inc
A src/mainboard/bytedance/bd_egs/acpi/platform.asl
A src/mainboard/bytedance/bd_egs/board.fmd
A src/mainboard/bytedance/bd_egs/board_info.txt
A src/mainboard/bytedance/bd_egs/bootblock.c
A src/mainboard/bytedance/bd_egs/devicetree.cb
A src/mainboard/bytedance/bd_egs/dsdt.asl
A src/mainboard/bytedance/bd_egs/gpio.c
A src/mainboard/bytedance/bd_egs/gpio.h
A src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h
A src/mainboard/bytedance/bd_egs/ramstage.c
A src/mainboard/bytedance/bd_egs/romstage.c
16 files changed, 782 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75722/6
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Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS6:
Build is failing again.
File src/mainboard/google/dedede/variants/baseboard/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75680/comment/4a5d6e2f_f1b080a5 :
PS6, Line 76: soc_config->tdp_pl4 = 0;
I don't think you need to zero this?
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Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email )
Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75681/comment/22c63b13_f1352d34 :
PS7, Line 29: 31
From the bug, I thought we're not setting PsysPl1 for dibbi?
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