coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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5387 discussions

[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by Reka Norman (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: ChiaLing, Paul Menzel, Ryan Lin, Subrata Banik, Sumeet R Pawnikar, Zhuohao Lee. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 7: (1 comment) File src/mainboard/google/dedede/variants/blipper/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75679/comment/0c5fb02c_f333492a : PS5, Line 62: register "power_limits_config" = "{ : .tdp_pl1_override = 6, : .tdp_pl2_override = 20, : }" > Hi Reka, […] I just want to make sure we're not changing the settings on existing dedede devices. Currently the baseboard doesn't set PL4, but with your change it will, so this affects all devices. If I understand correctly, 60W is the default, so if coreboot doesn't set PL4 it will be set to 60W. Is that right? I just checked a random dedede device and that seems to be the case. If so then I guess technically this would be fine, but I still think it's safer to keep the coreboot behaviour the same for exising devices, i.e. coreboot shouldn't set PL4. How about in the baseboard devicetree we don't set PL4, and dibbi variants can override it? -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 7 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 01:31:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config
by Kangheui Won (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Subrata Banik, Tarun Tuli. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75767?usp=email ) Change subject: {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75767?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5 Gerrit-Change-Number: 75767 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 00:37:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn
by Kangheui Won (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Subrata Banik, Tarun Tuli. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75768?usp=email ) Change subject: soc/intel/cmn/cse: Rename `cse_store_rw_fw_ver` helper fn ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0 Gerrit-Change-Number: 75768 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 00:35:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/myst: Update PCIE_RST_L drive
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75700?usp=email ) Change subject: mb/google/myst: Update PCIE_RST_L drive ...................................................................... mb/google/myst: Update PCIE_RST_L drive PCIE_RST_L is attached to a pull down, change the init to NC. BUG=None TEST=Boot to OS Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index f97cc16..d6cbe1e 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -52,7 +52,7 @@ PAD_NC(GPIO_24), /* GPIO_25-26: Not available */ /* SOC_PCIE_RST1_R_L */ - PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), + PAD_NC(GPIO_27), /* GPIO_28: Not available */ /* SD_AUX_RST */ PAD_GPO(GPIO_29, LOW), -- To view, visit https://review.coreboot.org/c/coreboot/+/75700?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639 Gerrit-Change-Number: 75700 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Update PCIe romstage gpios
by Eric Lai (Code Review) 13 Jun '23

13 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75699?usp=email ) Change subject: mb/google/myst: Update PCIe romstage gpios ...................................................................... mb/google/myst: Update PCIe romstage gpios Update PCIe GPIOs during rom stage to properly initialize the PCIe devices and allow the NVMe/eMMC to be properly detected. BUG=b:284213391 TEST=Boot to OS Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/myst/variants/baseboard/gpio.c 2 files changed, 14 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 108dd4e..6d0d0d6 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -54,8 +54,6 @@ .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, - /* TODO(b/284213391): Fix PCIe shutdown */ - .link_hotplug = 3, .clk_req = CLK_REQ3, }; @@ -68,8 +66,6 @@ .function_number = PCI_FUNC(NVME_DEVFN), .link_speed_capability = GEN_MAX, .turn_off_unused_lanes = true, - /* TODO(b/284213391): Fix PCIe shutdown */ - .link_hotplug = 3, .clk_req = CLK_REQ3, }; diff --git a/src/mainboard/google/myst/variants/baseboard/gpio.c b/src/mainboard/google/myst/variants/baseboard/gpio.c index efd654e..f97cc16 100644 --- a/src/mainboard/google/myst/variants/baseboard/gpio.c +++ b/src/mainboard/google/myst/variants/baseboard/gpio.c @@ -196,8 +196,22 @@ /* PCIE_RST needs to be brought high before FSP-M runs */ static const struct soc_amd_gpio romstage_gpio_table[] = { /* Deassert all AUX_RESET lines & PCIE_RST */ + /* SD_AUX_RST */ + PAD_GPO(GPIO_29, LOW), + /* SSD_AUX_RESET */ + PAD_GPO(GPIO_31, LOW), /* WLAN_AUX_RST_L (ACTIVE LOW) */ PAD_GPO(GPIO_38, HIGH), + /* WWAN_AUX_RST_L (ACTIVE LOW) */ + PAD_GPO(GPIO_39, HIGH), + /* CLK_REQ0_L / WLAN */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* CLK_REQ1_L / SD */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ2_L / WWAN */ + PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), + /* CLK_REQ3_L / SSD */ + PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/75699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Gerrit-Change-Number: 75699 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
by Sukumar Ghorai (Code Review) 13 Jun '23

13 Jun '23

Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75814?usp=email ) Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown ...................................................................... src/soc/intel/meteorlake: disable acpi timer for xtal shutdown acpi timer need to disable for both soc-pmc and ioe-pmc, required for xtal shutdown. xtal shutdown is a requirement for platform to enter deepest sleep s0i2.2. Change-Id: I4b5f8f6647364d967ed96c45fe5a9d55fdc8a2c7 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/soc/intel/meteorlake/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/75814/1 diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 790bf9c..32b1b2a 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -616,7 +616,7 @@ * 2) disabling the PM ACPI Timer. * We handle both by ourself! */ - s_cfg->EnableTcoTimer = 1; + s_cfg->EnableTcoTimer = 0; } static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/75814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5f8f6647364d967ed96c45fe5a9d55fdc8a2c7 Gerrit-Change-Number: 75814 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/rex: LZ4 compress ramstage instead of LZMA
by Karthik Ramasubramanian (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Jamie Ryu, Kapil Porwal, Paul Menzel, Raj Astekar, Tarun Tuli, Wonkyu Kim. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75769?usp=email ) Change subject: mb/google/rex: LZ4 compress ramstage instead of LZMA ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Tue, 13 Jun 2023 23:04:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits
by Felix Held (Code Review) 13 Jun '23

13 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75766?usp=email ) Change subject: soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits ...................................................................... soc/amd/common/cpu/noncar/cpu: rename get_smee_reserved_address_bits Rename get_smee_reserved_address_bits to get_sme_reserved_address_bits since the feature is called secure memory encryption and the last 'e' in SMEE bit in the SYSCFG MSR just stands for enable. The function will return a valid number of reserved address bits no matter if this is enabled or not, so drop the second 'e'. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75766 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/cpu.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index 891dece..eec593c 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -35,7 +35,7 @@ wrmsr(MSR_CSTATE_ADDRESS, cst_addr); } -static uint32_t get_smee_reserved_address_bits(void) +static uint32_t get_sme_reserved_address_bits(void) { if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE) return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & @@ -47,5 +47,5 @@ uint32_t get_usable_physical_address_bits(void) { - return cpu_phys_address_size() - get_smee_reserved_address_bits(); + return cpu_phys_address_size() - get_sme_reserved_address_bits(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3795f7a861e39cb6c8209fee10191f233cbcd308 Gerrit-Change-Number: 75766 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Pratikkumar V Prajapati (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Paul Menzel, Subrata Banik. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75625?usp=email ) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/75625/comment/cb36177d_b5bb2397 : PS3, Line 145: INTEL_TME_GEN_NEW_KEY_EACH_WARM_REBOOT > INTEL_TME_UPDATE_KEY_ON_WARM_BOOT or INTEL_TME_GENERATE_KEY_ON_WARM_BOOT renamed it, let me know. https://review.coreboot.org/c/coreboot/+/75625/comment/16816686_c7cbb15f : PS3, Line 155: INTEL_TME_EXCLUDE_CBMEM > how about the below name knowing this is file for intel common code hence, dropping the intel here. […] renamed it, let me know. -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 3 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 13 Jun 2023 22:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Pratikkumar V Prajapati (Code Review) 13 Jun '23

13 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75625?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... soc/intel/common: Introduce configs for TME exclusion range and new key generation Add following config options. 1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT Program Intel TME to generate a new key for each warm reboot. TME always generates a new key on each cold reboot. With this option enabled TME generates a new key even in warm reboot. Without this option TME reuses the key for warm reboot. 2. TME_EXCLUDE_CBMEM_ENCRYPTION Allows CBMEM to get excluded from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM does not get encrypted by TME. If TME is not programmed to generate a new key in warm reboot, exclusion range does not need be programmed due to the fact that TME uses same key in warm reboot if TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed to generate a new key in warm reboot, contents of the CBMEM get encrypted with a new key in each warm reboot case and that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM to get excluded from being encrypted and can be accessed in warm reboot case also. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75625/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2023