coreboot-gerrit June 2023

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[S] Change in coreboot[master]: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452
by Eric Lai (Code Review) 17 Jun '23

17 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75827?usp=email ) Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452 ...................................................................... mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452 This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the anx7452 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The anx7452 retimer does not appear to support this feature, so let the SoC do the flip. BUG=b:267589042,b:281006910 TEST=verified DP-ALT mode works on rex using both cable orientations Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/rex/variants/rex0/variant.c 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: Nick Vaccaro: Looks good to me, approved build bot (Jenkins): Verified Tarun Tuli: Looks good to me, approved Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/variant.c b/src/mainboard/google/rex/variants/rex0/variant.c index b259636..032eef9 100644 --- a/src/mainboard/google/rex/variants/rex0/variant.c +++ b/src/mainboard/google/rex/variants/rex0/variant.c @@ -6,6 +6,10 @@ #include <sar.h> #include <variant/gpio.h> +#define TCP2_AUX_SHIFT 4 +#define TCP_AUX_MASK 0x03 +#define TCP_AUX_FOLLOW_CC1 0x01 + const char *get_wifi_sar_cbfs_filename(void) { return "wifi_sar_0.hex"; @@ -26,4 +30,14 @@ { config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)); + + if (fw_config_probe(FW_CONFIG(DB_USB, USB4_ANX7452)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_ANX7452_V2))) { + /* + * Configure TCP2 for + * "SBU orientation not handled by external retimer" + */ + config->tcss_aux_ori &= ~(TCP_AUX_MASK << TCP2_AUX_SHIFT); + config->tcss_aux_ori |= TCP_AUX_FOLLOW_CC1 << TCP2_AUX_SHIFT; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Gerrit-Change-Number: 75827 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/myst: Update WWAN usb entry
by Eric Lai (Code Review) 17 Jun '23

17 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75819?usp=email ) Change subject: mb/google/myst: Update WWAN usb entry ...................................................................... mb/google/myst: Update WWAN usb entry USB3 is used for both typeA and WWAN based on different DB. BUG=b:287159026 TEST=change FW config and check typeA and WWAN can work. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Reviewed-on: https://review.coreboot.org/c/coreboot/+/75819 Reviewed-by: Tim Van Patten <timvp(a)google.com> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/myst/variants/baseboard/devicetree.cb 1 file changed, 15 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Tim Van Patten: Looks good to me, but someone else must approve Jon Murphy: Looks good to me, approved diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 01a4389..f4cae22 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -254,7 +254,21 @@ register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" register "group" = "ACPI_PLD_GROUP(1, 2)" - device ref usb3_port3 on end + device ref usb3_port3 on + probe DAUGHTERBOARD DB_B + end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_6)" + register "enable_delay_ms" = "20" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_11)" + register "reset_off_delay_ms" = "20" + device ref usb3_port3 on + probe WWAN WWAN_FM101GL + end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" @@ -293,25 +307,6 @@ end end end - device ref xhci_1 on - chip drivers/usb/acpi - register "type" = "UPC_TYPE_HUB" - device ref xhci_1_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_6)" - register "enable_delay_ms" = "20" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_11)" - register "reset_off_delay_ms" = "20" - device ref usb3_port7 on - probe WWAN WWAN_FM101GL - end - end - end - end - end device ref acp on end # Audio Processor (ACP) device ref mp2 on end # Sensor Fusion Hub (MP2) end -- To view, visit https://review.coreboot.org/c/coreboot/+/75819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Gerrit-Change-Number: 75819 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/gothrax: Generate RAM IDs for new memory parts
by Eric Lai (Code Review) 17 Jun '23

17 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75834?usp=email ) Change subject: mb/google/nissa/var/gothrax: Generate RAM IDs for new memory parts ...................................................................... mb/google/nissa/var/gothrax: Generate RAM IDs for new memory parts Add the support RAM parts for gothrax. Here is the ram part number list: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H58G56AK6BX069 1 (0001) K3LKBKB0BM-MGCP 2 (0010) BUG=b:284388714 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834 Reviewed-by: Henry Sun <henrysun(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc M src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt 3 files changed, 18 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve Henry Sun: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc index eace2e4..d3c1f68 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/gothrax/memory/Makefile.inc @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/gothrax/memory src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = H58G56AK6BX069 +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt index fa24790..7db6e24 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/gothrax/memory/dram_id.generated.txt @@ -1 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/gothrax/memory src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +H58G56AK6BX069 1 (0001) +K3LKBKB0BM-MGCP 2 (0010) diff --git a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt index 9621137..d26ec66 100644 --- a/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/gothrax/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name + +MT62F512M32D2DR-031 WT:B, +H58G56AK6BX069,*1 +K3LKBKB0BM-MGCP, -- To view, visit https://review.coreboot.org/c/coreboot/+/75834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Gerrit-Change-Number: 75834 Gerrit-PatchSet: 4 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/meteorlake: Update tcss_usb3 alias
by Eric Lai (Code Review) 17 Jun '23

17 Jun '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75892?usp=email ) Change subject: soc/intel/meteorlake: Update tcss_usb3 alias ...................................................................... soc/intel/meteorlake: Update tcss_usb3 alias TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb M src/mainboard/google/rex/variants/rex0/overridetree.cb M src/mainboard/google/rex/variants/screebo/overridetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb M src/soc/intel/meteorlake/chipset.cb M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/meteorlake/retimer.c 8 files changed, 39 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index bb13833..e15a7c4 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -67,21 +67,21 @@ register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))" - device ref tcss_usb3_port3 on end + device ref tcss_usb3_port2 on end end end end @@ -89,19 +89,19 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port0 as dfp[0].typec_port device generic 0 on end end chip drivers/intel/usb4/retimer register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port2 as dfp[1].typec_port + use tcss_usb3_port1 as dfp[1].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end end @@ -197,17 +197,17 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port1 as usb3_port + use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port1 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port - use tcss_usb3_port3 as usb3_port + use tcss_usb3_port2 as usb3_port device generic 2 alias conn2 on end end end diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 4619cba..9a37ac4 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -323,14 +323,14 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port3 on end + device ref tcss_usb3_port2 on end end end end @@ -338,14 +338,14 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port0 as dfp[0].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end end @@ -781,12 +781,12 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port1 as usb3_port + use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port3 as usb3_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 8669d95..e6c8a9c 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -256,14 +256,14 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port4 on end + device ref tcss_usb3_port3 on end end end end @@ -271,14 +271,14 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port2 as dfp[0].typec_port + use tcss_usb3_port1 as dfp[0].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port4 as dfp[0].typec_port + use tcss_usb3_port3 as dfp[0].typec_port device generic 0 on end end end @@ -518,12 +518,12 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port4 as usb3_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 66f2179..05a61be 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -220,25 +220,25 @@ register "desc" = ""USB3 Type-C Port C0"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(4, 2)" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(3, 2)" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" - device ref tcss_usb3_port3 on end + device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C3"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 2)" - device ref tcss_usb3_port4 on end + device ref tcss_usb3_port3 on end end end end @@ -246,24 +246,24 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port0 as dfp[0].typec_port device generic 0 on end end chip drivers/intel/usb4/retimer register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port2 as dfp[1].typec_port + use tcss_usb3_port1 as dfp[1].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end chip drivers/intel/usb4/retimer register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port4 as dfp[1].typec_port + use tcss_usb3_port3 as dfp[1].typec_port device generic 0 on end end end diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb index f51f18b..3f1579e 100644 --- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb @@ -15,22 +15,22 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port1 as usb3_port + use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port1 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port - use tcss_usb3_port3 as usb3_port + use tcss_usb3_port2 as usb3_port device generic 2 alias conn2 on end end chip drivers/intel/pmc_mux/conn use usb2_port4 as usb2_port - use tcss_usb3_port4 as usb3_port + use tcss_usb3_port3 as usb3_port device generic 3 alias conn3 on end end end diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 57d1205..6a9c26a 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -57,16 +57,16 @@ register "type" = "UPC_TYPE_HUB" device usb 0.0 alias tcss_root_hub off chip drivers/usb/acpi - device usb 3.0 alias tcss_usb3_port1 off end + device usb 3.0 alias tcss_usb3_port0 off end end chip drivers/usb/acpi - device usb 3.1 alias tcss_usb3_port2 off end + device usb 3.1 alias tcss_usb3_port1 off end end chip drivers/usb/acpi - device usb 3.2 alias tcss_usb3_port3 off end + device usb 3.2 alias tcss_usb3_port2 off end end chip drivers/usb/acpi - device usb 3.3 alias tcss_usb3_port4 off end + device usb 3.3 alias tcss_usb3_port3 off end end end end diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 790bf9c..30800e6 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -413,10 +413,10 @@ const struct soc_intel_meteorlake_config *config) { const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port0), DEV_PTR(tcss_usb3_port1), DEV_PTR(tcss_usb3_port2), DEV_PTR(tcss_usb3_port3), - DEV_PTR(tcss_usb3_port4), }; s_cfg->TcssAuxOri = config->tcss_aux_ori; diff --git a/src/soc/intel/meteorlake/retimer.c b/src/soc/intel/meteorlake/retimer.c index 3fd9c2d..269620d 100644 --- a/src/soc/intel/meteorlake/retimer.c +++ b/src/soc/intel/meteorlake/retimer.c @@ -10,10 +10,10 @@ int ec_port = 0; const struct device *tcss_port_arr[] = { + DEV_PTR(tcss_usb3_port0), DEV_PTR(tcss_usb3_port1), DEV_PTR(tcss_usb3_port2), DEV_PTR(tcss_usb3_port3), - DEV_PTR(tcss_usb3_port4), }; for (uint8_t i = 0; i < MAX_TYPE_C_PORTS; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/75892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Gerrit-Change-Number: 75892 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/yavilla: Update eMMC DLL settings
by Tony Huang (Code Review) 17 Jun '23

17 Jun '23

Tony Huang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75894?usp=email ) Change subject: mb/google/nissa/var/yavilla: Update eMMC DLL settings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99524fc04dd086f7839434e6ccd842e2495d367 Gerrit-Change-Number: 75894 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: mb/google/nissa/var/yavilla: Update eMMC DLL settings
by Tony Huang (Code Review) 17 Jun '23

17 Jun '23

Attention is currently required from: Chen-Tsung Hsieh, Tarun Tuli. Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75894?usp=email ) Change subject: mb/google/nissa/var/yavilla: Update eMMC DLL settings ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: We got 0x00 errro when testing samsung 64G emmc. Sorry for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/75894?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic99524fc04dd086f7839434e6ccd842e2495d367 Gerrit-Change-Number: 75894 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Comment-Date: Sat, 17 Jun 2023 02:27:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/var/taeko: Enable CsPiStartHighinEct
by Joey Peng (Code Review) 17 Jun '23

17 Jun '23

Joey Peng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75825?usp=email ) Change subject: mb/google/brya/var/taeko: Enable CsPiStartHighinEct ...................................................................... Abandoned Will upload to CHROMIUM directly -- To view, visit https://review.coreboot.org/c/coreboot/+/75825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If546b1259597c8025902e8f31b659ebee6f98eb3 Gerrit-Change-Number: 75825 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: ec/google/chromeec: Use mux_conn to get the right USB port
by Eric Lai (Code Review) 17 Jun '23

17 Jun '23

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik, Tarun Tuli, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75824?usp=email ) Change subject: ec/google/chromeec: Use mux_conn to get the right USB port ...................................................................... Patch Set 2: (1 comment) File src/ec/google/chromeec/ec_acpi.c: https://review.coreboot.org/c/coreboot/+/75824/comment/a42c0383_7b40d674 : PS1, Line 15: #include "drivers/intel/pmc_mux/conn/chip.h" > #include <drivers/intel/pmc_mux/conn/chip. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a Gerrit-Change-Number: 75824 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Sat, 17 Jun 2023 00:31:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: doc/Makefile: Fix build dir setting
by Nicholas Chin (Code Review) 17 Jun '23

17 Jun '23

Attention is currently required from: Elyes Haouas, Felix Held, Felix Singer, Jan Samek, Martin L Roth. Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75893?usp=email ) Change subject: doc/Makefile: Fix build dir setting ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > It seems it already worked before... @Felix Singer: Before commit 4d8da8ed, running something like `make sphinx BUILDDIR=my_build_dir` in the Documentation already seems to override any BUILDDIR variable in the Makefiles. So I guess the question is why we are fixing a change that may not have been needed in the first place. According to https://www.gnu.org/software/make/manual/html_node/Overriding.html, command line arguments override any ordinary assignments in the Makefile (despite not using `?=`) -- To view, visit https://review.coreboot.org/c/coreboot/+/75893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc44134cf1996592597252aeb9dcf7ffb3378ee3 Gerrit-Change-Number: 75893 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 17 Jun 2023 00:10:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: doc/Makefile: Fix build dir setting
by Nico Huber (Code Review) 17 Jun '23

17 Jun '23

Attention is currently required from: Elyes Haouas, Felix Held, Felix Singer, Jan Samek, Martin L Roth. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75893?usp=email ) Change subject: doc/Makefile: Fix build dir setting ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > That commit mainly adds the parameter `BUILDDIR` to the Sphinx make command. It seems it already worked before... -- To view, visit https://review.coreboot.org/c/coreboot/+/75893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc44134cf1996592597252aeb9dcf7ffb3378ee3 Gerrit-Change-Number: 75893 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 16 Jun 2023 22:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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