coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: [WIP] mb/google: Re-arrange mainboard_smi_sleep()
by Kyösti Mälkki (Code Review) 16 Jun '23

16 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74604?usp=email ) Change subject: [WIP] mb/google: Re-arrange mainboard_smi_sleep() ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74604?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Gerrit-Change-Number: 74604 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: [WIP] mb/google: Use chromeec_smi_sleep()
by Kyösti Mälkki (Code Review) 16 Jun '23

16 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74605?usp=email ) Change subject: [WIP] mb/google: Use chromeec_smi_sleep() ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74605?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6 Gerrit-Change-Number: 74605 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree ...
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Eric Lai, Felix Singer, Jan Samek, Mario Scheithauer, Michał Żygowski, Nico Huber, Piotr Król, Subrata Banik. Hello Arthur Heymans, Elyes Haouas, Eric Lai, Jan Samek, Mario Scheithauer, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75871?usp=email to look at the new patch set (#4). Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree option ...................................................................... [RFC] soc/intel/skylake: Use boolean type for s0ix_enable devicetree option Mainboards which use that option are found by this line: grep -Er "SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" mainboard | cut -d ':' -f 1 | awk -F '[/]' '{print $1"/"$2"/"$3}' | xargs grep -r "s0ix_enable" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/skylake/chip.h 12 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/75871/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Michael Niewöhner (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Eric Lai, Felix Singer, Jan Samek, Mario Scheithauer, Michał Żygowski, Nico Huber, Piotr Król, Subrata Banik. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Patchset: PS3: me likes PS3: > > If we do this at a bigger scale, I would prefer an enum. Then it could […] I agree with Felix and don't see a reason for a enum tbh -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 20:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: [WIP] SMBIOS: Move identification strings
by Kyösti Mälkki (Code Review) 16 Jun '23

16 Jun '23

Kyösti Mälkki has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/74452?usp=email ) Change subject: [WIP] SMBIOS: Move identification strings ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/74452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a8199b4a5482984dd7fdde67e90acca5af5ca6 Gerrit-Change-Number: 74452 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: drivers/intel/fsp2_0: Read MRC version from FSP binary
by Subrata Banik (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Andrey Petrov, Hannah Williams, Paul Menzel, Ronak Kanabar, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75524?usp=email ) Change subject: drivers/intel/fsp2_0: Read MRC version from FSP binary ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: > @Ronak, can you please allow me to land the MRC version API? > > i have made some changes and that is more scalable https://review.coreboot.org/c/coreboot/+/75899 as WIP CL for your sight. I will try to split the cl into multiple applicable cls. -- To view, visit https://review.coreboot.org/c/coreboot/+/75524?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f7b536929eafae692f0c1fad6ca15e4021dccd8 Gerrit-Change-Number: 75524 Gerrit-PatchSet: 12 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 20:08:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Use MRC version for storing MRC cache instead FSP version
by Subrata Banik (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Andrey Petrov, Kapil Porwal, Tarun Tuli. Hello Andrey Petrov, Kapil Porwal, Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75899?usp=email to look at the new patch set (#2). Change subject: Use MRC version for storing MRC cache instead FSP version ...................................................................... Use MRC version for storing MRC cache instead FSP version So far FSP version is getting used to store the MRC cache hence, MRC cache is getting erase and retrain the memory with every FSP uprev (irrespective of whether MRC is being uprev'ed or not) TEST=Try below scenarios on google/rex FSP version: 0D.00.7B.41 MRC version: 07.12.01 update the FSP version alone (w/o changing the MRC version) uprev FSP version: 0D.00.7B.42 MRC version: 07.12.01 w/o this patch: Result: Retrain the complete memory as coreboot erased the mrc cache due to FSP version mismatch. [SPEW ] MRC no cache found [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [DEBUG] MRC: 'RW_MRC_CACHE' need update. [DEBUG] Reference Code - MRC = 0.7.12.1 w/ this patch: Result: Utilize the existing MRC cache and skip memory retraining. Improve the user experience during in-field FW update where save boot time by not doing memory training as MRC is not being updated although FSP is getting uprev'ed. [DEBUG] FMAP: area RW_MRC_CACHE found @ 1710000 (65536 bytes) [INFO ] MRC: Hash idx 0x100d comparison successful. [SPEW ] MRC cache found, size 53829 bytes [DEBUG] FMAP: area RW_MRC_CACHE found @ 1710000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [DEBUG] MRC: 'RW_MRC_CACHE' does not need update. [DEBUG] Reference Code - MRC = 0.7.12.1 ... ... [DEBUG] MRC VERSION 3. 0x75ffeb60 0x00000004 Change-Id: I82faac3fe600d2b37103e25357f6cf3c2310875c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/save_mrc_data.c M src/soc/intel/meteorlake/Kconfig 6 files changed, 82 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/75899/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82faac3fe600d2b37103e25357f6cf3c2310875c Gerrit-Change-Number: 75899 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: Use MRC version for storing MRC cache instead FSP version
by Subrata Banik (Code Review) 16 Jun '23

16 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75899?usp=email ) Change subject: Use MRC version for storing MRC cache instead FSP version ...................................................................... Use MRC version for storing MRC cache instead FSP version So far FSP version is getting used to store the MRC cache hence, MRC cache is getting erase and retrain the memory with every FSP uprev (irrespective of whether MRC is being uprev'ed or not) TEST=Try below scenarios on google/rex FSP version: 0D.00.7B.41 MRC version: 07.18.01 update the FSP version alone (w/o changing the MRC version) uprev FSP version: 0D.00.7B.42 MRC version: 07.18.01 w/o this patch: Result: Retrain the complete memory as coreboot erased the mrc cache due to FSP version mismatch. w/ this patch: Result: Utilize the existing MRC cache and skip memory retraining. Improve the user experience during in-field FW update where save boot time by not doing memory training as MRC is not being updated although FSP is getting uprev'ed. Change-Id: I82faac3fe600d2b37103e25357f6cf3c2310875c Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/save_mrc_data.c M src/soc/intel/meteorlake/Kconfig 6 files changed, 82 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/75899/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 5080812..fd752b0 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -27,6 +27,7 @@ #define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052 #define CBMEM_ID_FSP_RUNTIME 0x52505346 #define CBMEM_ID_FSPM_VERSION 0x56505346 +#define CBMEM_ID_MRC_VERSION 0x5f43524d #define CBMEM_ID_GDT 0x4c474454 #define CBMEM_ID_HOB_POINTER 0x484f4221 #define CBMEM_ID_IGD_OPREGION 0x4f444749 @@ -112,6 +113,7 @@ { CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \ { CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \ { CBMEM_ID_FSPM_VERSION, "FSPM VERSION" }, \ + { CBMEM_ID_MRC_VERSION, "MRC VERSION" }, \ { CBMEM_ID_GDT, "GDT " }, \ { CBMEM_ID_HOB_POINTER, "HOB " }, \ { CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \ diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 378f4fb..310bac7 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -402,4 +402,12 @@ reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR status. +config FSP_HEADER_HAS_MRC_VERSION_INFO + bool + default n + help + Select this Kconfig if FSP binary for platforms that have MRC version part of + FSP_PRODUCER_DATA_TABLES. FSP_PRODUCER_DATA_TABLES defined in `FspProducerDataHeader.h` + file. + endif diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 02cd4e0..40110a6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -27,6 +27,10 @@ #include <Base.h> #include <FspmUpd.h> #include <FspsUpd.h> +#if CONFIG(FSP_HEADER_HAS_MRC_VERSION_INFO) +#define BUILD_TIME_STAMP_SIZE 12 +#include <FspProducerDataHeader.h> +#endif #if CONFIG(DISPLAY_FSP_VERSION_INFO) #include <FirmwareVersionInfoHob.h> #elif CONFIG(DISPLAY_FSP_VERSION_INFO_2) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 6d25844..39fa963 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -30,10 +30,11 @@ static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); -static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) +static void do_fsp_post_memory_init(bool s3wake, uint32_t version) { struct range_entry fsp_mem; uint32_t *fsp_version_cbmem; + uint32_t *mrc_version_cbmem; fsp_find_reserved_memory(&fsp_mem); @@ -56,20 +57,29 @@ (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request!\n"); - /* ramstage uses the FSP-M version when updating the MRC cache */ if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake) { - fsp_version_cbmem = cbmem_add(CBMEM_ID_FSPM_VERSION, - sizeof(fsp_version)); - if (!fsp_version_cbmem) - printk(BIOS_ERR, "Failed to add FSP-M version to cbmem.\n"); - *fsp_version_cbmem = fsp_version; + if (CONFIG(FSP_HEADER_HAS_MRC_VERSION_INFO)) { + /* ramstage uses the MRC version when updating the MRC cache */ + mrc_version_cbmem = cbmem_add(CBMEM_ID_MRC_VERSION, + sizeof(version)); + if (!mrc_version_cbmem) + printk(BIOS_ERR, "Failed to add MRC version to cbmem.\n"); + *mrc_version_cbmem = version; + } else { + /* ramstage uses the FSP-M version when updating the MRC cache */ + fsp_version_cbmem = cbmem_add(CBMEM_ID_FSPM_VERSION, + sizeof(version)); + if (!fsp_version_cbmem) + printk(BIOS_ERR, "Failed to add FSP-M version to cbmem.\n"); + *fsp_version_cbmem = version; + } } /* Create romstage handof information */ romstage_handoff_init(s3wake); } -static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) +static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t version) { void *data; size_t mrc_size; @@ -82,7 +92,7 @@ /* Assume boot device is memory mapped. */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, fsp_version, + data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, version, &mrc_size); if (data == NULL) return; @@ -134,7 +144,7 @@ } static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, - bool s3wake, uint32_t fsp_version, + bool s3wake, uint32_t version, const struct memranges *memmap) { /* @@ -152,7 +162,7 @@ return CB_ERR; } - fsp_fill_mrc_cache(arch_upd, fsp_version); + fsp_fill_mrc_cache(arch_upd, version); /* Configure bootmode */ if (s3wake) { @@ -210,19 +220,51 @@ struct memranges memmap; }; +#if CONFIG(FSP_HEADER_HAS_MRC_VERSION_INFO) +/* + * Helper function to read MRC version + * + * There are multiple ways to read the MRC version using + * Intel FSP. Currently the only supported method to read + * MRC by reading the FSP_PRODUCER_DATA_TABLES (part of the + * FSP binary). + */ +static uint32_t fsp_mrc_version(void) +{ + uint32_t ver = 0; + size_t fspm_blob_size; + void *fspm_blob_file = cbfs_map(CONFIG_FSP_M_CBFS, &fspm_blob_size); + if (!fspm_blob_file) + return 0; + + FSP_PRODUCER_DATA_TABLES *ft = fspm_blob_file + FSP_HDR_OFFSET; + FSP_PRODUCER_DATA_TYPE2 *table2 = &ft->FspProduceDataType2; + size_t mrc_version_size = sizeof(table2->MrcVersion); + for (size_t i = 0; i < mrc_version_size; i++) { + ver |= (table2->MrcVersion[i] << ((mrc_version_size - 1) - i) * 8); + } + cbfs_unmap(fspm_blob_file); + return ver; +} +#endif + static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) { uint32_t status; fsp_memory_init_fn fsp_raminit; FSPM_UPD fspm_upd, *upd; FSPM_ARCH_UPD *arch_upd; - uint32_t fsp_version; + uint32_t version; const struct fsp_header *hdr = &context->header; const struct memranges *memmap = &context->memmap; post_code(POST_MEM_PREINIT_PREP_START); - fsp_version = fsp_memory_settings_version(hdr); + version = fsp_memory_settings_version(hdr); +#if CONFIG(FSP_HEADER_HAS_MRC_VERSION_INFO) + version = fsp_mrc_version(); + printk(BIOS_ERR, "Subrata MRC version = %x\n", version); +#endif upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); @@ -254,7 +296,7 @@ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); /* Fill common settings on behalf of chipset. */ - if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, + if (fsp_fill_common_arch_params(arch_upd, s3wake, version, memmap) != CB_SUCCESS) die_with_post_code(POST_INVALID_VENDOR_BINARY, "FSPM_ARCH_UPD not found!\n"); @@ -266,7 +308,7 @@ #endif /* Give SoC and mainboard a chance to update the UPD */ - platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); + platform_fsp_memory_init_params_cb(&fspm_upd, version); /* * For S3 resume case, if valid mrc cache data is not found or @@ -309,7 +351,7 @@ "FspMemoryInit returned with error 0x%08x!\n", status); } - do_fsp_post_memory_init(s3wake, fsp_version); + do_fsp_post_memory_init(s3wake, version); /* * fsp_debug_after_memory_init() checks whether the end of the tolum diff --git a/src/drivers/intel/fsp2_0/save_mrc_data.c b/src/drivers/intel/fsp2_0/save_mrc_data.c index 8550b68..830f10a8 100644 --- a/src/drivers/intel/fsp2_0/save_mrc_data.c +++ b/src/drivers/intel/fsp2_0/save_mrc_data.c @@ -11,14 +11,18 @@ { size_t mrc_data_size; const void *mrc_data; - uint32_t *fspm_version; + uint32_t *version; if (acpi_is_wakeup_s3()) return; - fspm_version = cbmem_find(CBMEM_ID_FSPM_VERSION); - if (!fspm_version) { - printk(BIOS_ERR, "Failed to read FSP-M version from cbmem.\n"); + if (CONFIG(FSP_HEADER_HAS_MRC_VERSION_INFO)) + version = cbmem_find(CBMEM_ID_MRC_VERSION); + else + version = cbmem_find(CBMEM_ID_FSPM_VERSION); + + if (!version) { + printk(BIOS_ERR, "Failed to read FSP-M/MRC version from cbmem.\n"); return; } @@ -34,7 +38,7 @@ * code which saves the data to flash doesn't write if the latest * training data matches this one. */ - if (mrc_cache_stash_data(MRC_TRAINING_DATA, *fspm_version, mrc_data, + if (mrc_cache_stash_data(MRC_TRAINING_DATA, *version, mrc_data, mrc_data_size) < 0) printk(BIOS_ERR, "Failed to stash MRC data\n"); } diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 0bcbcf2..80915a9 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -117,6 +117,7 @@ select X86_CLFLUSH_CAR select X86_INIT_NEED_1_SIPI select INTEL_KEYLOCKER + select FSP_HEADER_HAS_MRC_VERSION_INFO config SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT bool -- To view, visit https://review.coreboot.org/c/coreboot/+/75899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82faac3fe600d2b37103e25357f6cf3c2310875c Gerrit-Change-Number: 75899 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/kahlee: Enable secure OS
by CoolStar (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: CoolStar, Felix Held, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75874?usp=email ) Change subject: mb/google/kahlee: Enable secure OS ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Ack, I don't have a Grunt to test. […] if you are testing Windows on grunt, these commits https://github.com/MrChromebox/coreboot/commit/b25929e08ebfed5fec54b19aa50a… will let you boot windows https://github.com/MrChromebox/coreboot/commit/830831f517e8779c5acc9b36a171… -- To view, visit https://review.coreboot.org/c/coreboot/+/75874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3 Gerrit-Change-Number: 75874 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 16 Jun 2023 19:23:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: mb/google/kahlee: Enable secure OS
by Jon Murphy (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: CoolStar, Felix Held, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75874?usp=email ) Change subject: mb/google/kahlee: Enable secure OS ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/kahlee/Kconfig: https://review.coreboot.org/c/coreboot/+/75874/comment/2df08032_b52c1ba5 : PS4, Line 148: c > nit: ChromeOS Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/75874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3 Gerrit-Change-Number: 75874 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 16 Jun 2023 19:23:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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