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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75729/comment/8a00c2a6_5d82b2c6 :
PS2, Line 23: HId
> HID
Done
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 4:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/75729/comment/46dcaee7_710cbea9 :
PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
: assert(dev != NULL);
> Hmmm, looks like we always set `.ops` for the domain? Technically, it's like
> any other pointer in there. The difference is that the others are already
> set (all 21 times). Even if it feels 21 lines too much, it would also feel
> odd to handle this one pointer differently. Or maybe I misunderstand.
>
> That dummy device you have in mind, could that be added by sconfig?
> Runtime code seems overkill.
Looks like I found a better place in DSDT.
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Hello Angel Pons, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Nico Huber, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
acpi: Move ECAM resource below PNP0C02 device in a common place
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HId device needs to reserve this region.
As no AMD platforms has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table so that Linux in such a way that it prevents Linux from using PCIe
ECAM. This change fixes that problem.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
---
M src/acpi/dsdt_top.asl
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/soc/intel/apollolake/acpi/northbridge.asl
M src/soc/intel/baytrail/acpi/southcluster.asl
M src/soc/intel/braswell/acpi/southcluster.asl
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/denverton_ns/acpi/northcluster.asl
M src/soc/intel/skylake/acpi/systemagent.asl
14 files changed, 23 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75729/5
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
acpi: Move ECAM resource below PNP0C02 device in a common place
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HId device needs to reserve this region.
As no AMD platforms has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table so that Linux in such a way that it prevents Linux from using PCIe
ECAM. This change fixes that problem.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
---
M src/acpi/acpi.c
M src/acpi/dsdt_top.asl
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/soc/intel/apollolake/acpi/northbridge.asl
M src/soc/intel/baytrail/acpi/southcluster.asl
M src/soc/intel/braswell/acpi/southcluster.asl
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/denverton_ns/acpi/northcluster.asl
M src/soc/intel/skylake/acpi/systemagent.asl
15 files changed, 25 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75729/4
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Change subject: arch/x86/smbios: Add a config string for BIOS Vendor in SMBIOS Type 0
......................................................................
Patch Set 4:
(3 comments)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/75737/comment/dd7b3d9d_ef02affd :
PS2, Line 894: BIOS_VENDOR
> I don't see why. Type 0 is not about the mainboard.
The other attributes and methods related to the type0 table don't start with MAINBOARD_ as well. So I also prefer to remove the MAINBOARD_ prefix.
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/75737/comment/ff843bfb_ecd0bc18 :
PS4, Line 895: string
: prompt "SMBIOS BIOS Vendor string"
To align with the style of the other options below, please write like it like this.
```
prompt "SMBIOS BIOS Vendor"
string
```
https://review.coreboot.org/c/coreboot/+/75737/comment/8996a2b7_c6e8ca12 :
PS4, Line 899: string
Same here, please remove.
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Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs
......................................................................
Patch Set 12: Code-Review+1
(2 comments)
File src/mainboard/bytedance/bd_egs/Kconfig:
https://review.coreboot.org/c/coreboot/+/75722/comment/de88b685_8ba7974a :
PS10, Line 32: default "\\_SB.C%03d"
> Done
As I mentioned it's uncommon to override this at the mainboard
level. I had a closer look and it changes `C%03X` to `C%03d`,
i.e. limiting the values to only 3-digit decimals. I don't under-
stand why this would be necessary.
Please wait for the reviewer when closing comment threads, if
there is any doubt.
File src/mainboard/bytedance/bd_egs/gpio.h:
https://review.coreboot.org/c/coreboot/+/75722/comment/6fa38baa_65e12003 :
PS8, Line 18: PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
> Done
Thanks!
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Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/brya/variants/gothrax/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75872/comment/88d37965_d76cc10f :
PS4, Line 1: # SPDX-License-Identifier: GPL-2.0-only
> Afaik coreboot doesn't use license headers for Makefiles anymore.
Done
File src/mainboard/google/brya/variants/gothrax/memory.c:
https://review.coreboot.org/c/coreboot/+/75872/comment/34b0cbab_aa12a4d3 :
PS4, Line 15: gpio_t spd_gpios[] = {
> same like base board, no need.
OK, we have removed it.
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Change subject: mb/{cfl,cml,whl}: Use true/false macros for RMT dt option
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> For Chili, it's most likely that I didn't know yet what it is when […]
Will do that in a separate patch series.
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Change subject: mb/{cfl,cml,whl}: Use true/false macros for RMT dt option
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Patch Set 1:
(1 comment)
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PS1:
> Some people also want to add them for documentation. Not sure about our policy about that.
For Chili, it's most likely that I didn't know yet what it is when
copying the option. So feel free to drop that.
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Change subject: Makefile.inc: fix multiple jobs build issue
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Patch Set 5:
(1 comment)
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PS5:
> *ping*
AFAICT, yes, for everything that goes through our `stage-y += ` mechanism.
I just grepped `fmap_config.h` and it seems to be a lot. Thanks for the
thoroughness.
Should we put that in a follow-up?
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