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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75729/comment/80d6b4cc_b543d9da :
PS6, Line 27: so that Linux in such a way that it prevents
> Sounds confusing. I would rephrase like: […]
I would just drop the first "so that Linux", it seems to be the
spurious part.
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 15:
(1 comment)
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/75756/comment/07e5c61d_8ace3dfb :
PS15, Line 363: .
Option name strings should not end with a period
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75729/comment/4e120cef_dd3a88b2 :
PS6, Line 25: platforms
typo: platform
https://review.coreboot.org/c/coreboot/+/75729/comment/f8641292_9b343163 :
PS6, Line 27: so that Linux in such a way that it prevents
Sounds confusing. I would rephrase like:
```
so that Linux is prevented from using PCIe ECAM.
```
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Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
This patch implements APIs to access the FW versions in CMOS. The get
API allows users to retrieve the current version from CMOS memory.
The set API allows users to set the version in CMOS memory.
BUG=b:280722061
TEST=APIs verified on nivviks and marasov board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/cse_lite_cmos.c
A src/soc/intel/common/block/cse/cse_lite_cmos.h
4 files changed, 220 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74995/47
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Change subject: new port for Lenovo L420 laptop
......................................................................
Patch Set 4:
(14 comments)
Patchset:
PS4:
Hi Nicolas. Thanks for your contribution and welcome to coreboot! 😊
Looks pretty good from the first look. I suggested some clean ups.
File src/mainboard/lenovo/l420/Kconfig:
https://review.coreboot.org/c/coreboot/+/75992/comment/4fcfa03b_9ba88927 :
PS4, Line 24: # Workaround for EC/KBC.
remove the empty line and this comment
https://review.coreboot.org/c/coreboot/+/75992/comment/7ba87d71_6c4c6b66 :
PS4, Line 27: # Realtek 8168
remove the empty line and this comment
https://review.coreboot.org/c/coreboot/+/75992/comment/9a525310_06e0f965 :
PS4, Line 55: int
no need to redefine the type, please remove
https://review.coreboot.org/c/coreboot/+/75992/comment/ab2bc0d4_4fe487c0 :
PS4, Line 59: int
no need to redefine the type, please remove
https://review.coreboot.org/c/coreboot/+/75992/comment/025da419_861673cf :
PS4, Line 63: string
no need to redefine the type, please remove
https://review.coreboot.org/c/coreboot/+/75992/comment/598978b6_67f1e484 :
PS4, Line 75: config WARNINGS_ARE_ERRORS
: default n
:
: config PAYLOAD_CONFIGFILE
: default
These shouldn't be in the mainboard Kconfig, please remove.
File src/mainboard/lenovo/l420/board_info.txt:
https://review.coreboot.org/c/coreboot/+/75992/comment/d1285b42_e6dd4597 :
PS4, Line 5: Flashrom support: n
probably y?
File src/mainboard/lenovo/l420/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/75992/comment/440a4750_8467a6b1 :
PS4, Line 29: # IGD Displays (spread spectrum on)
: register "gfx" = "GMA_STATIC_DISPLAYS(1)"
:
: # Enable DisplayPort Hotplug with 6ms pulse
: register "gpu_dp_d_hotplug" = "0x06"
:
: # Enable Panel as LVDS and configure power delays
: register "gpu_panel_port_select" = "PANEL_PORT_LVDS"
: register "gpu_panel_power_cycle_delay" = "6"
: register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms
: register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
: register "gpu_panel_power_backlight_on_delay" = "2500" # T3: 200ms
: register "gpu_panel_power_backlight_off_delay" = "2500" # T4: 200ms
: register "gpu_cpu_backlight" = "0x1155"
: r
Move these under the IGD controller
https://review.coreboot.org/c/coreboot/+/75992/comment/73834483_1c052463 :
PS4, Line 45: device domain 0 on
Sandybridge has a chipset device tree (at src/northbridge/intel/sandybridge/chipset.cb) with alias names for the PCI devices. Please use the names for your configuration, which allows to remove most of the comments like "Integrated Graphics Controller" since the names are self explaining.
PCI devices which are turned off can simply be left out.
Example usage for 02.0:
```
device ref igd on end
```
File src/mainboard/lenovo/l420/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/75992/comment/b117fbb4_70a82205 :
PS4, Line 24: // global NVS and variables
seems superfluous, remove
https://review.coreboot.org/c/coreboot/+/75992/comment/35fbb98b_6b5597ec :
PS4, Line 28: Scope (\_SB) {
: Device (PCI0)
: {
: #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
: #include <southbridge/intel/bd82x6x/acpi/pch.asl>
: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
: }
: }
```
Device (\_SB.PCI0)
{
...
}
```
File src/mainboard/lenovo/l420/mainboard.c:
https://review.coreboot.org/c/coreboot/+/75992/comment/c46e7ac3_837afb27 :
PS4, Line 9: // mainboard_enable is executed as first thing after
: // enumerate_buses().
seems superfluous, remove
File src/mainboard/lenovo/l420/smihandler.c:
https://review.coreboot.org/c/coreboot/+/75992/comment/7510ab47_92acaacd :
PS4, Line 13: /* FIXME: check this */
checked?
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Change subject: soc/intel/cmd/blk/cse: Use common firmware partitionn data structure
......................................................................
soc/intel/cmd/blk/cse: Use common firmware partitionn data structure
This patch updates local define firmware partition version with common
data-structure.
BUG=b:280722061
Test=Verified the changes on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ia27ff72a244d1f4872059c5ee7433e36fa55d963
---
M src/soc/intel/common/block/cse/cse_lite_cmos.c
1 file changed, 7 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/75896/7
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Change subject: soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
......................................................................
soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
During a cold reboot, the CBMEM memory resets and loses the stored
firmware versions. This causes the firmware versions to be fetched again
from the CSE, which increases the boot time by about 200 ms. This patch
stores a backup of the firmware version in CMOS and updates the CBMEM
memory during a cold reboot.
BUG=b:280722061
Test=Verified the changes on nissa board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ibc5a027aa2bb7217e5032f56fece0846783557a5
---
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/cse/cse_lite_cmos.h
2 files changed, 64 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/75755/18
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Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
This patch implements APIs to access the FW versions in CMOS. The get
API allows users to retrieve the current version from CMOS memory.
The set API allows users to set the version in CMOS memory.
BUG=b:280722061
TEST=APIs verified on nivviks and marasov board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/cse_lite_cmos.c
A src/soc/intel/common/block/cse/cse_lite_cmos.h
4 files changed, 220 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74995/46
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