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Change subject: mb/google/nissa/var/gothrax: Initialise overridetree
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/gothrax/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/76013/comment/2a07e841_845882b9 :
PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
: register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
: register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
: register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
:
: register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
:
> Please move these under the XHCI controller.
Done
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 6:
(1 comment)
File src/acpi/dsdt_top.asl:
https://review.coreboot.org/c/coreboot/+/75729/comment/82e7e3ec_c5dd673b :
PS6, Line 60: Method
`iasl` complains about the return value. But I don't think it needs a method.
It could also be `Name (_CRS, ResourceTemplate () { ...` I guess.
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 6: -Code-Review
(1 comment)
Patchset:
PS6:
I'm quite confused why some boards build others don't...
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 6: Code-Review+1
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75729/comment/0bfd3b25_3b30e4dc :
PS6, Line 27:
Could break the line here to get a perfect block :)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/75729/comment/9a4eaaf9_ed7e3cb6 :
PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
: assert(dev != NULL);
> > Hmmm, looks like we always set `.ops` for the domain? Technically, it's like […]
I kind of rememeberd that we have a `dsdt_top` now :D but there's
even the right `if` already, amazing!
I've checked with a little bash foo that we always include it, looks
good:
```
$ diff -u <(git grep -l dsdt_top.asl) <(git ls-files \*/dsdt.asl)
--- /dev/fd/63 2023-06-21 12:08:33.095420956 +0200
+++ /dev/fd/62 2023-06-21 12:08:33.098754243 +0200
@@ -182,4 +182,3 @@
src/mainboard/system76/tgl-u/dsdt.asl
src/mainboard/system76/whl-u/dsdt.asl
src/mainboard/up/squared/dsdt.asl
-util/autoport/main.go
```
https://review.coreboot.org/c/coreboot/+/75729/comment/f0958517_ed793085 :
PS2, Line 594: 1
> It should be unique among "PNP0C02" devices. I don't think we need _UID here. […]
Done
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Change subject: arch/x86,lib: Migrate SMBIOS implementation to common code
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75886/comment/d2801eb3_3fe1de5a :
PS3, Line 11: code define
nit: sounds confusing to me. Is there a comma missing?
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Change subject: mb/google/nissa/var/gothrax: Initialise overridetree
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/gothrax/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/76013/comment/d9ebf4ef_4e757655 :
PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
: register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
: register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
: register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
:
: register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1
:
Please move these under the XHCI controller.
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 6:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/75729/comment/91417dac_4c0a397b :
PS2, Line 594: 1
> It should be unique among "PNP0C02" devices. I don't think we need _UID here. […]
Done
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Hello Angel Pons, Felix Held, Jeff Daly, Lance Zhao, Matt DeVillier, Nico Huber, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified-1 by build bot (Jenkins)
Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
acpi: Move ECAM resource below PNP0C02 device in a common place
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
If the operating system does not natively comprehend reserving the
MMCFG region, the MMCFG region must be reserved by firmware. The
address range reported in the MCFG table or by _CBA method (see Section
4.1.3) must be reserved by declaring a motherboard resource. For most
systems, the motherboard resource would appear at the root of the ACPI
namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
the resources in this case should not be claimed in the root PCI bus’s
_CRS. The resources can optionally be returned in Int15 E820 or
EFIGetMemoryMap as reserved memory but must always be reported through
ACPI as a motherboard resource.
So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.
As no AMD platforms has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table so that Linux in such a way that it prevents Linux from using PCIe
ECAM. This change fixes that problem.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
---
M src/acpi/dsdt_top.asl
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/acpi/hostbridge.asl
M src/northbridge/intel/i945/acpi/i945.asl
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/pineview/acpi/pineview.asl
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
M src/soc/intel/apollolake/acpi/northbridge.asl
M src/soc/intel/baytrail/acpi/southcluster.asl
M src/soc/intel/braswell/acpi/southcluster.asl
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/denverton_ns/acpi/northcluster.asl
M src/soc/intel/skylake/acpi/systemagent.asl
14 files changed, 23 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/75729/6
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Change subject: acpi: Move ECAM resource below PNP0C02 device in a common place
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75729/comment/543b9a4f_7d083018 :
PS2, Line 28: unknown reason
> in the seabios case (depthcharge probably too) this area is covered by one e820 reserved address ran […]
Done
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Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com>
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Gerrit-Comment-Date: Wed, 21 Jun 2023 10:00:16 +0000
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