coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Yunlong Jia (Code Review) 25 Jun '23

25 Jun '23

Attention is currently required from: Felix Singer, Tarun Tuli. Yunlong Jia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/3cdf815e_6fcdd3cf : PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN : : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 : > Done Where is the XHCI you mentioned? -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 2 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Sun, 25 Jun 2023 02:17:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: nb/intel/pineview: Drop unused attributes from sysinfo struct
by Felix Singer (Code Review) 25 Jun '23

25 Jun '23

Attention is currently required from: Angel Pons, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76098?usp=email ) Change subject: nb/intel/pineview: Drop unused attributes from sysinfo struct ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76098/comment/dbbb5fc3_76febb1b : PS1, Line 7: Clean sysinfo > Suggestion: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Gerrit-Change-Number: 76098 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 25 Jun 2023 01:02:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS description
by Yuchen He (Code Review) 24 Jun '23

24 Jun '23

Yuchen He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76047?usp=email ) Change subject: commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS description ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76047/comment/3f1eb4df_1db99650 : PS2, Line 7: Change > I guess this counts as a fix ;) So let's say "fix" instead of "change" Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Gerrit-Change-Number: 76047 Gerrit-PatchSet: 2 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Jun 2023 22:26:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS description
by Yuchen He (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Yuchen He. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76047?usp=email to look at the new patch set (#3). Change subject: commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS description ...................................................................... commonlib/post_codes.h: Fix POST_EXIT_PCI_SCAN_BUS description Description of POST_EXIT_PCI_SCAN_BUS indicates the opposite of what its name suggests. Secondly, POST_ENTER_PCI_SCAN_BUS and POST_EXIT_PCI_SCAN_BUS have identical comments, which appears to be a copy-paste issue. Change the description accordingly. Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Signed-off-by: lilacious <yuchenhe126(a)gmail.com> --- M src/commonlib/include/commonlib/console/post_codes.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/76047/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/76047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Gerrit-Change-Number: 76047 Gerrit-PatchSet: 3 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[master]: commonlib/post_codes.h: Change POST_EXIT_PCI_SCAN_BUS description
by Felix Singer (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Yuchen He. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76047?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: commonlib/post_codes.h: Change POST_EXIT_PCI_SCAN_BUS description ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76047/comment/9a0874a8_998b28fa : PS2, Line 7: Change I guess this counts as a fix ;) So let's say "fix" instead of "change" -- To view, visit https://review.coreboot.org/c/coreboot/+/76047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Gerrit-Change-Number: 76047 Gerrit-PatchSet: 2 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Comment-Date: Sat, 24 Jun 2023 21:57:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6
by Felix Singer (Code Review) 24 Jun '23

24 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76080?usp=email ) Change subject: util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6 ...................................................................... util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6 Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76080 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum D util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum A util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum 11 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9f86995..25ddc86 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ BINUTILS_VERSION=2.40 IASL_VERSION=20230331 # CLANG version number -CLANG_VERSION=16.0.5 +CLANG_VERSION=16.0.6 CMAKE_VERSION=3.26.4 NASM_VERSION=2.16.01 diff --git a/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 04f2648..0000000 --- a/util/crossgcc/sum/clang-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ad47162ae20fdd85e2db27e1a00a989c88dcacbe tarballs/clang-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..1a4e21e --- /dev/null +++ b/util/crossgcc/sum/clang-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +f005e3b6d41cf92c083d2a16960aaeb1a6e3c76c tarballs/clang-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 8e5cd8c..0000000 --- a/util/crossgcc/sum/clang-tools-extra-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -38f9ca678f40617f760b4da5795e92be0e6d573b tarballs/clang-tools-extra-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..939dda2 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +41c06d541cfcc126ddc344e7f162148f2ecf0461 tarballs/clang-tools-extra-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum deleted file mode 100644 index d78ef2d..0000000 --- a/util/crossgcc/sum/cmake-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -3330310405697793ec3d24a63233e22713e1c808 tarballs/cmake-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..a7aeb57 --- /dev/null +++ b/util/crossgcc/sum/cmake-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +0de534cfef38697e115c3ae80634765f05e78e5b tarballs/cmake-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 72c7ae4..0000000 --- a/util/crossgcc/sum/compiler-rt-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6db2ebf9a345a8e42011888359de65aea37c75ba tarballs/compiler-rt-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..d79eab8 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +28ddc89aac54cbfa6d0a0cd07a14bbd3f3a01d5f tarballs/compiler-rt-16.0.6.src.tar.xz diff --git a/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum b/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum deleted file mode 100644 index 84e1e56..0000000 --- a/util/crossgcc/sum/llvm-16.0.5.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ce2c4a55b249a3076e89c31d920f06a65510c4dc tarballs/llvm-16.0.5.src.tar.xz diff --git a/util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum b/util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum new file mode 100644 index 0000000..f8185f1 --- /dev/null +++ b/util/crossgcc/sum/llvm-16.0.6.src.tar.xz.cksum @@ -0,0 +1 @@ +072d2fb4b10f95d06189de00eb7f7e9b35c54e9a tarballs/llvm-16.0.6.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/76080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f Gerrit-Change-Number: 76080 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: nb/intel/pineview: Drop unused attributes from sysinfo struct
by Elyes Haouas (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Angel Pons, Elyes Haouas. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76098?usp=email to look at the new patch set (#2). Change subject: nb/intel/pineview: Drop unused attributes from sysinfo struct ...................................................................... nb/intel/pineview: Drop unused attributes from sysinfo struct Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/pineview/raminit.h 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/76098/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Gerrit-Change-Number: 76098 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: nb/intel/pineview/raminit.h: Clean sysinfo
by Felix Singer (Code Review) 24 Jun '23

24 Jun '23

Attention is currently required from: Angel Pons, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76098?usp=email ) Change subject: nb/intel/pineview/raminit.h: Clean sysinfo ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76098/comment/8064259a_351ffe16 : PS1, Line 7: Clean sysinfo Suggestion: `Drop unused attributes from sysinfo struct` -- To view, visit https://review.coreboot.org/c/coreboot/+/76098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Gerrit-Change-Number: 76098 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 24 Jun 2023 21:30:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/cannonlake/chip.h: Use boolean type where applicable
by Felix Singer (Code Review) 24 Jun '23

24 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75959?usp=email ) Change subject: soc/intel/cannonlake/chip.h: Use boolean type where applicable ...................................................................... soc/intel/cannonlake/chip.h: Use boolean type where applicable Change-Id: If9639bd1d0737f94931c28b0e12f214a5c1f87c0 Signed-off-by: lilacious <yuchenhe126(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75959 Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/intel/cannonlake/chip.h 1 file changed, 64 insertions(+), 63 deletions(-) Approvals: Jonathon Hall: Looks good to me, but someone else must approve build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index e8d46d4..3093050 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -10,6 +10,7 @@ #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/power_limit.h> +#include <stdbool.h> #include <stdint.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -57,12 +58,12 @@ /* S0ix configuration */ /* Enable S0iX support */ - int s0ix_enable; + bool s0ix_enable; /* Enable Audio DSP oscillator qualification for S0ix */ - uint8_t cppmvric2_adsposcdis; + bool cppmvric2_adsposcdis; /* Enable DPTF support */ - int dptf_enable; + bool dptf_enable; enum { MAX_PC_DEFAULT = 0, @@ -78,10 +79,10 @@ } max_package_c_state; /* Deep SX enable for both AC and DC */ - int deep_s3_enable_ac; - int deep_s3_enable_dc; - int deep_s5_enable_ac; - int deep_s5_enable_dc; + bool deep_s3_enable_ac; + bool deep_s3_enable_dc; + bool deep_s5_enable_ac; + bool deep_s5_enable_dc; /* Deep Sx Configuration * DSX_EN_WAKE_PIN - Enable WAKE# pin @@ -107,7 +108,7 @@ } SaGv; /* Rank Margin Tool. 1:Enable, 0:Disable */ - uint8_t RMT; + bool RMT; /* USB related */ struct usb2_port_config usb2_ports[16]; @@ -117,7 +118,7 @@ /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; /* USB2 PHY power gating */ - uint8_t PchUsb2PhySusPgDisable; + bool PchUsb2PhySusPgDisable; /* SATA related */ enum { @@ -133,39 +134,39 @@ SataDevSlpDswReset = 7 } SataDevSlpRstConfig; - uint8_t SataSalpSupport; - uint8_t SataPortsEnable[8]; - uint8_t SataPortsDevSlp[8]; + bool SataSalpSupport; + bool SataPortsEnable[8]; + bool SataPortsDevSlp[8]; uint8_t SataPortsDevSlpResetConfig[8]; - uint8_t SataPortsHotPlug[8]; + bool SataPortsHotPlug[8]; /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ - uint8_t SlpS0WithGbeSupport; + bool SlpS0WithGbeSupport; /* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */ - uint8_t PchPmSlpS0VmRuntimeControl; + bool PchPmSlpS0VmRuntimeControl; /* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */ - uint8_t PchPmSlpS0Vm070VSupport; + bool PchPmSlpS0Vm070VSupport; /* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */ - uint8_t PchPmSlpS0Vm075VSupport; + bool PchPmSlpS0Vm075VSupport; /* Audio related */ - uint8_t PchHdaDspEnable; + bool PchHdaDspEnable; /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ - uint8_t PchHdaAudioLinkHda; - uint8_t PchHdaIDispCodecDisconnect; - uint8_t PchHdaAudioLinkDmic0; - uint8_t PchHdaAudioLinkDmic1; - uint8_t PchHdaAudioLinkSsp0; - uint8_t PchHdaAudioLinkSsp1; - uint8_t PchHdaAudioLinkSsp2; - uint8_t PchHdaAudioLinkSndw1; - uint8_t PchHdaAudioLinkSndw2; - uint8_t PchHdaAudioLinkSndw3; - uint8_t PchHdaAudioLinkSndw4; + bool PchHdaAudioLinkHda; + bool PchHdaIDispCodecDisconnect; + bool PchHdaAudioLinkDmic0; + bool PchHdaAudioLinkDmic1; + bool PchHdaAudioLinkSsp0; + bool PchHdaAudioLinkSsp1; + bool PchHdaAudioLinkSsp2; + bool PchHdaAudioLinkSndw1; + bool PchHdaAudioLinkSndw2; + bool PchHdaAudioLinkSndw3; + bool PchHdaAudioLinkSndw4; /* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ @@ -174,18 +175,18 @@ * clksrc. */ uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Implemented as slot or built-in? */ - uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ - uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* * Enable/Disable AER (Advanced Error Reporting) for Root Port * 0: Disable AER * 1: Enable AER */ - uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; /* PCIE RP ASPM, ASPM support for the root port */ enum { @@ -204,23 +205,23 @@ } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; /* eMMC and SD */ - uint8_t ScsEmmcHs400Enabled; + bool ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ - uint8_t EmmcHs400DllNeed; + bool EmmcHs400DllNeed; /* 0-39: number of active delay for RX strobe, unit is 125 psec */ uint8_t EmmcHs400RxStrobeDll1; /* 0-78: number of active delay for TX data, unit is 125 psec */ uint8_t EmmcHs400TxDataDll; /* Enable/disable SD card write protect pin configuration on CML */ - uint8_t ScsSdCardWpPinEnabled; + bool ScsSdCardWpPinEnabled; /* Heci related */ - uint8_t DisableHeciRetry; + bool DisableHeciRetry; /* Gfx related */ - uint8_t SkipExtGfxScan; + bool SkipExtGfxScan; - uint8_t Device4Enable; + bool Device4Enable; /* CPU PL2/4 Config * Performance: Maximum PLs for maximum performance. @@ -234,13 +235,13 @@ struct vr_config domain_vr_config[NUM_VR_DOMAINS]; /* Enables support for Teton Glacier hybrid storage device */ - uint8_t TetonGlacierMode; + bool TetonGlacierMode; /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ - uint8_t eist_enable; + bool eist_enable; /* Enable C6 DRAM */ - uint8_t enable_c6dram; + bool enable_c6dram; /* * SLP_S3 Minimum Assertion Width Policy @@ -346,14 +347,14 @@ unsigned int sdcard_cd_gpio; /* Enable Pch iSCLK */ - uint8_t pch_isclk; + bool pch_isclk; /* * Acoustic Noise Mitigation * 0b - Disable * 1b - Enable noise mitigation */ - uint8_t AcousticNoiseMitigation; + bool AcousticNoiseMitigation; /* * Disable Fast Package C-state ramping @@ -361,10 +362,10 @@ * 0b - Enabled * 1b - Disabled */ - uint8_t FastPkgCRampDisableIa; - uint8_t FastPkgCRampDisableGt; - uint8_t FastPkgCRampDisableSa; - uint8_t FastPkgCRampDisableFivr; + bool FastPkgCRampDisableIa; + bool FastPkgCRampDisableGt; + bool FastPkgCRampDisableSa; + bool FastPkgCRampDisableFivr; /* * Adjust the VR slew rates @@ -380,32 +381,32 @@ uint8_t SlowSlewRateForFivr; /* SATA Power Optimizer */ - uint8_t satapwroptimize; + bool satapwroptimize; /* SATA Gen3 Strength */ struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX]; /* Enable or disable eDP device */ - uint8_t DdiPortEdp; + bool DdiPortEdp; /* Enable or disable HPD of DDI port B/C/D/F */ - uint8_t DdiPortBHpd; - uint8_t DdiPortCHpd; - uint8_t DdiPortDHpd; - uint8_t DdiPortFHpd; + bool DdiPortBHpd; + bool DdiPortCHpd; + bool DdiPortDHpd; + bool DdiPortFHpd; /* Enable or disable DDC of DDI port B/C/D/F */ - uint8_t DdiPortBDdc; - uint8_t DdiPortCDdc; - uint8_t DdiPortDDdc; - uint8_t DdiPortFDdc; + bool DdiPortBDdc; + bool DdiPortCDdc; + bool DdiPortDDdc; + bool DdiPortFDdc; /* Unlock all GPIO Pads */ - uint8_t PchUnlockGpioPads; + bool PchUnlockGpioPads; /* Enable GBE wakeup */ - uint8_t LanWakeFromDeepSx; - uint8_t WolEnableOverride; + bool LanWakeFromDeepSx; + bool WolEnableOverride; #if !CONFIG(SOC_INTEL_COMETLAKE) uint32_t VrPowerDeliveryDesign; @@ -416,7 +417,7 @@ * 0: Use FSP default GPIO PM program, * 1: coreboot to override GPIO PM program */ - uint8_t gpio_override_pm; + bool gpio_override_pm; /* * GPIO PM configuration: 0 to disable, 1 to enable power gating * Bit 6-7: Reserved -- To view, visit https://review.coreboot.org/c/coreboot/+/75959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9639bd1d0737f94931c28b0e12f214a5c1f87c0 Gerrit-Change-Number: 75959 Gerrit-PatchSet: 4 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: commonlib/post_codes.h: Change POST_EXIT_PCI_SCAN_BUS description
by Yuchen He (Code Review) 24 Jun '23

24 Jun '23

Yuchen He has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76047?usp=email ) Change subject: commonlib/post_codes.h: Change POST_EXIT_PCI_SCAN_BUS description ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76047/comment/c01d82bb_d4e83400 : PS1, Line 12: an error. > rather say copy-paste issue. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc Gerrit-Change-Number: 76047 Gerrit-PatchSet: 2 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 24 Jun 2023 19:34:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023