coreboot-gerrit May 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Joey Peng (Code Review) 02 May '23

02 May '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Paul Menzel, Nick Vaccaro, Eric Lai. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74727/comment/906f3eef_9d59635c PS9, Line 9: Disable C1E on RPL CPUs > Could you add more description for what the reason to do it? Enable C1E will cause what issue etc.. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 11 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:24:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Joey Peng (Code Review) 02 May '23

02 May '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Paul Menzel, Nick Vaccaro. Hello build bot (Jenkins), YH Lin, Tarun Tuli, Subrata Banik, Nick Vaccaro, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74727 to look at the new patch set (#11). Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... soc/intel/alderlake: Disable C1E on RPL CPUs Since disabling C1E could improve acoustic noise for RPL, add judgement in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs . BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74727/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 11 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC
by Dtrain Hsu (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jamie Chen, Tarun Tuli, Kyle Lin, Nick Vaccaro. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74880 ) Change subject: mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Gerrit-Change-Number: 74880 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:22:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Joey Peng (Code Review) 02 May '23

02 May '23

Attention is currently required from: YH Lin, Tarun Tuli, Subrata Banik, Paul Menzel, Nick Vaccaro. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/74727/comment/52999aaa_17fcc4a9 PS9, Line 1013: s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion; > would you please give one new line before ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 10 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:20:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Joey Peng (Code Review) 02 May '23

02 May '23

Attention is currently required from: YH Lin, Tarun Tuli, Joey Peng, Paul Menzel, Nick Vaccaro. Hello build bot (Jenkins), YH Lin, Tarun Tuli, Subrata Banik, Nick Vaccaro, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74727 to look at the new patch set (#10). Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... soc/intel/alderlake: Disable C1E on RPL CPUs Disable C1E on RPL CPUs BUG=b:278654939 TEST:emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74727/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 10 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC
by Derek Huang (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jamie Chen, Tarun Tuli, Kyle Lin, Nick Vaccaro. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74880 ) Change subject: mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Gerrit-Change-Number: 74880 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:17:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC
by Subrata Banik (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jamie Chen, Tarun Tuli, Derek Huang, Kyle Lin, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74880 ) Change subject: mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPEC ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Gerrit-Change-Number: 74880 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kyle Lin <kylelinck(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:16:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/microcode: Implement microcode info caching inside cbmem
by Subrata Banik (Code Review) 02 May '23

02 May '23

Attention is currently required from: Tarun Tuli, Reka Norman, Kapil Porwal, Julius Werner, Arthur Heymans, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74873 ) Change subject: cpu/intel/microcode: Implement microcode info caching inside cbmem ...................................................................... Patch Set 4: (4 comments) Patchset: PS3: > I assume this patch is in response to b/242473942? And your time savings aren't really from "searching", they're from bypassing CBFS verification? > > If we determined that we actually *want* to bypass CBFS verification, and that it is safe to do so, there are more straight-forward ways to do that (e.g. cbfs_unverified_area_map()). But my understanding from the previous discussion on the bug was that we don't actually want to do that because there could actually be some attack vector here (even if it's e.g. just a rollback attack). In that case, we obviously also can't do something like this. yes, your understanding is correct that we don't want to bypass the CBFS verification check File src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h: https://review.coreboot.org/c/coreboot/+/74873/comment/52db6492_7d2fadff PS3, Line 89: 0x55434f44 > Note that this spells DOCU in little endian, if you were aiming for UCOD you need to flip it. Ack File src/cpu/intel/microcode/microcode.c: https://review.coreboot.org/c/coreboot/+/74873/comment/5529cdf6_5f3df87a PS3, Line 295: if (ENV_CREATES_CBMEM) > Why this? If you want this to only execute in RAMSTAGE, I think just wrapping the whole thing in `#if ENV_RAMSTAGE` would be clearer. should be avoided. done with latest patch set https://review.coreboot.org/c/coreboot/+/74873/comment/b28ca67d_85193481 PS3, Line 305: info->microcode_ptr = (uintptr_t)find_cbfs_microcode(); > Is this just stashing a pointer to MMIO flash across reboots? That sounds like a bad idea. What if you get a firmware update in between where CBFS files can randomly move around? > > Besides, what is the security story for this feature? CBMEM cannot be trusted across reboots, it could have been manipulated by any attacker trying to gain persistence (e.g. just point this at a random unused part of flash outside of CBFS and put a malicious microcode blob there). Is there some separate verification check for this microcode later on that we trust? Added the checksum now, hopefully this is good to avoid a scenario where `just point this at a random unused part of flash outside of CBFS and put a malicious microcode blob there`. Please let me know your thoughts -- To view, visit https://review.coreboot.org/c/coreboot/+/74873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Gerrit-Change-Number: 74873 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:10:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/microcode: Implement microcode info caching inside cbmem
by build bot (Jenkins) (Code Review) 02 May '23

02 May '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Reka Norman, Kapil Porwal, Arthur Heymans, Lean Sheng Tan. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74873 ) Change subject: cpu/intel/microcode: Implement microcode info caching inside cbmem ...................................................................... Patch Set 4: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175360): https://review.coreboot.org/c/coreboot/+/74873/comment/7f61e561_c8b11180 PS4, Line 6: Possible long commit subject (prefer a maximum 65 characters) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175360): https://review.coreboot.org/c/coreboot/+/74873/comment/08d5fc67_c6d3819d PS4, Line 34: microcode: Update skipped, already up-to-date Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Gerrit-Change-Number: 74873 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:08:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/microcode: Implement microcode info caching inside cbmem
by Subrata Banik (Code Review) 02 May '23

02 May '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Reka Norman, Kapil Porwal, Arthur Heymans, Lean Sheng Tan. Hello build bot (Jenkins), Tarun Tuli, Reka Norman, Kapil Porwal, Arthur Heymans, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74873 to look at the new patch set (#4). Change subject: cpu/intel/microcode: Implement microcode info caching inside cbmem ...................................................................... cpu/intel/microcode: Implement microcode info caching inside cbmem This patch implements microcode info caching inside cbmem (during ramstage) to avoid boot time penalty. Currently, locating ucode from cbfs is a continuous process in every boot hence, there are boot time penalties knowing typically `cpu_microcode_blob.bin` is consists of multiple microcodes as per different CPU steppings. Adding more microcode into `cpu_microcode_blob.bin` would increase the boot time cost. Hence, this patch enables caching of microcode related information inside cbmem that can be used to avoid microcode searching time during the warm resets. Additionally, use a tab to align `CBMEM_ID_CSE_PARTITION_VERSION` with other CBMEM ID macros. TEST=Build and boot google/rex with this patch which saves 20ms of boot time. Without this patch during warm reset: cbmem -c | grep microcode CBFS: Found 'cpu_microcode_blob.bin' @0x1e180 size 0x35400 in mcache @0x76add080 microcode: sig=0x906a4 pf=0x80 revision=0x423 microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date boot time: 10:start of ramstage 982,231 (43) 971:loading FSP-S 1,003,633 (21,402) With this patch during warm reset: cbmem -c | grep microcode microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date boot time: 10:start of ramstage 981,061 (45) 971:loading FSP-S 982,134 (1,072) Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/cpu/intel/microcode/microcode.c M src/include/cpu/intel/microcode.h 3 files changed, 110 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74873/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I208a2e0e1dce96b2d4d63f882e8aaf4c25f77e3f Gerrit-Change-Number: 74873 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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