coreboot-gerrit May 2023

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[M] Change in coreboot[master]: soc/intel/common: Introduce API to get the FSP Reset Status
by Subrata Banik (Code Review) 02 May '23

02 May '23

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74783 ) Change subject: soc/intel/common: Introduce API to get the FSP Reset Status ...................................................................... soc/intel/common: Introduce API to get the FSP Reset Status This patch creates a function to read the FSP API Reset Status. This function relies on the FSP Scheduled Reset HOB which holds the reset type (warm/cold/shutdown) information along with any platform specific reset need (like global reset). Ideally FSP API should be able to return the status (both success and error code) upon exiting the FSP API but unfortunately there are some scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return any ERROR status. Hence, this function provides an additional hook to read the FSP reset status by reading the dedicated HOB without relying on the FSP API exit status code. Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option to handle broken FSP API return status issue. Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config will call into this newly added API to get the FSP return status from MultiPhaseSiInit. BUG=b:278665768 TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC code and call into this API to know the return status from MultiPhaseSiInit FSP API. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/common/fsp_reset.c M src/soc/intel/common/reset.h 3 files changed, 130 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 2132737..378f4fb 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -389,4 +389,17 @@ Save MRC training data after FSP-S. Select this on platforms that generate MRC cache HOB data as part of FSP-S rather than FSP-M. +config FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN + bool + default n + depends on PLATFORM_USES_FSP2_2 + help + Select this config for Intel SoC platform where FSP MultiPhaseSiInit API is unable + to return ERROR status properly. + + The config option will be selected based on the target SoC platform and if the + problem existed inside the FSP MultiPhaseSiInit. At present the problem has only + reported with Alder Lake and Raptor Lake FSP where MultiPhaseSiInit API is unable + to return any ERROR status. + endif diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index bf265515..3a34aad 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -1,10 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/reset.h> #include <stdint.h> +static const uint8_t fsp_reset_guid[16] = { + 0xff, 0x97, 0x05, 0xea, 0x58, 0x88, 0xca, 0x41, + 0xbb, 0xc1, 0xfe, 0x18, 0xfc, 0xd2, 0x8e, 0x22 +}; + +static const uint8_t fsp_global_reset_guid[16] = { + 0x4c, 0x1b, 0xb3, 0x9d, 0xef, 0xf5, 0xbb, 0x48, + 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 +}; + +/* Platform Reset String as per Intel FSP is "PCH RESET" in unicode */ +#define PLATFORM_RESET_STRING_LENGTH 20 + +struct pch_reset_data { + char reserved[PLATFORM_RESET_STRING_LENGTH]; + efi_guid_t global_reset_uid; +}; + +/* This structure is used to provide information about PCH Reset */ +struct fsp_reset_hob { + EFI_RESET_TYPE reset_type; + struct pch_reset_data reset_data; +}; + void chipset_handle_reset(uint32_t status) { if (status == CONFIG_FSP_STATUS_GLOBAL_RESET) { @@ -15,3 +40,47 @@ printk(BIOS_ERR, "unhandled reset type %x\n", status); die("unknown reset type"); } + +static uint32_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type) +{ + uint32_t status; + + switch (reset_type) { + case EfiResetCold: + status = FSP_STATUS_RESET_REQUIRED_COLD; + break; + case EfiResetWarm: + status = FSP_STATUS_RESET_REQUIRED_WARM; + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", reset_type); + die("unknown reset type"); + } + + return status; +} + +/* + * Return PCH Reset Status + * The return status can be between EfiResetCold, EfiResetWarm, EfiResetShutdown + * or EfiResetPlatformSpecific. + * + * If reset type is `EfiResetPlatformSpecific` then relying on pch_reset_data structure + * to know if the reset type is a global reset. + */ +uint32_t fsp_get_pch_reset_status(void) +{ + assert(CONFIG(FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN)); + + size_t size; + const struct fsp_reset_hob *hob = fsp_find_extension_hob_by_guid(fsp_reset_guid, &size); + if (!hob) + return 0; + + if ((hob->reset_type == EfiResetPlatformSpecific) && + fsp_guid_compare((void *)&(hob->reset_data.global_reset_uid), + fsp_global_reset_guid)) + return CONFIG_FSP_STATUS_GLOBAL_RESET; + + return fsp_reset_type_to_status(hob->reset_type); +} diff --git a/src/soc/intel/common/reset.h b/src/soc/intel/common/reset.h index e1f6aab..d9c6ac6 100644 --- a/src/soc/intel/common/reset.h +++ b/src/soc/intel/common/reset.h @@ -13,4 +13,14 @@ /* Prepare for reset, run do_global_reset(), halt. */ __noreturn void global_reset(void); +/* + * Return PCH Reset Status + * The return status can be between EfiResetCold, EfiResetWarm, EfiResetShutdown + * or EfiResetPlatformSpecific. + * + * If reset type if `EfiResetPlatformSpecific` then relying on pch_reset_data structure + * to know if the reset type is a global reset. + */ +uint32_t fsp_get_pch_reset_status(void); + #endif /* _INTEL_COMMON_RESET_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Gerrit-Change-Number: 74783 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit
by Himanshu Sahdev (Code Review) 02 May '23

02 May '23

Attention is currently required from: Subrata Banik, Derek Huang, Andrey Petrov. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74784 ) Change subject: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/74784/comment/86905fb3_e621ce94 PS5, Line 199: status = fsp_get_pch_reset_status(); > > You aren't actually be reading the status from the dedicated HOB if it doesn't exists for some rea […] Got it! -- To view, visit https://review.coreboot.org/c/coreboot/+/74784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa Gerrit-Change-Number: 74784 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 02 May 2023 10:36:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Disable C1E on RPL CPUs
by Subrata Banik (Code Review) 02 May '23

02 May '23

Attention is currently required from: YH Lin, Tarun Tuli, Joey Peng, Paul Menzel, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74727 ) Change subject: soc/intel/alderlake: Disable C1E on RPL CPUs ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342 Gerrit-Change-Number: 74727 Gerrit-PatchSet: 11 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 May 2023 10:03:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common: Introduce API to get the FSP Reset Status
by Subrata Banik (Code Review) 02 May '23

02 May '23

Attention is currently required from: Derek Huang, Paul Menzel, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74783 ) Change subject: soc/intel/common: Introduce API to get the FSP Reset Status ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74783/comment/dc20ec6c_88ec5a50 PS2, Line 14: Ideally FSP API should be able to return the status (both success and : error code) upon exiting the FSP API but unfortunately there are some : scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return : any ERROR status. Hence, this function provides an additional hook to : read the FSP reset status by reading the dedicated HOB without relying : on the FSP API exit status code. > > > Is there an FSP upstream bug report for this? If yes, it’d be great if you referenced it. > > > > the bug being mentioned in the commit msg is the own assigned to Intel and there will be external communication from Intel > > Ping! marking this closed after 1 week. -- To view, visit https://review.coreboot.org/c/coreboot/+/74783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae Gerrit-Change-Number: 74783 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 02 May 2023 09:50:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit
by Subrata Banik (Code Review) 02 May '23

02 May '23

Attention is currently required from: Derek Huang, Himanshu Sahdev, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74784 ) Change subject: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/74784/comment/438ab4d7_225ec26a PS5, Line 199: status = fsp_get_pch_reset_status(); > You aren't actually be reading the status from the dedicated HOB if it doesn't exists for some reason (https://review.coreboot.org/c/coreboot/+/74783/5/src/soc/intel/common/fsp_r…) and will lose the last status from multi_phase_si_init as well. The meaning of HOB not found is not any *accidental reason* as i could sense from your above comment "it doesn't exist for some reason ". ``` const struct fsp_reset_hob *hob = fsp_find_extension_hob_by_guid(fsp_reset_guid, &size); if (!hob) return 0; ``` The meaning of reset info hob not found inside is like, FSP doesn't want to issue any reset during the boot hence, didn't populate the reset info hob. This can be assumed as everything is good hence, returning the status as 0 aka no reset required. for more details follow the fsp_handle_reset() > > Is setting status to 0 is intentional here in case !hob? Yes for sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/74784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa Gerrit-Change-Number: 74784 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 02 May 2023 09:49:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/speedstep: Use acpigen_write_processor_device()
by build bot (Jenkins) (Code Review) 02 May '23

02 May '23

Attention is currently required from: Nico Huber, Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74441 ) Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... Patch Set 4: (4 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175363): https://review.coreboot.org/c/coreboot/+/74441/comment/5614b86e_a441569b PS4, Line 11: The entries for duty_width and duty_offset are replaced with _PTC entry, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175363): https://review.coreboot.org/c/coreboot/+/74441/comment/97a0849a_ec55ec10 PS4, Line 16: apple/macbook21, dell/e6400, getac/p470, lenovo/t400, lenovo/t60, Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175363): https://review.coreboot.org/c/coreboot/+/74441/comment/fa8838d4_a0d5c167 PS4, Line 22: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-175363): https://review.coreboot.org/c/coreboot/+/74441/comment/cb92af92_a9ab9963 PS4, Line 27: Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 02 May 2023 09:26:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: cpu/intel/speedstep: Use acpigen_write_processor_device()
by Kyösti Mälkki (Code Review) 02 May '23

02 May '23

Attention is currently required from: Nico Huber, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74441 to look at the new patch set (#4). Change subject: cpu/intel/speedstep: Use acpigen_write_processor_device() ...................................................................... cpu/intel/speedstep: Use acpigen_write_processor_device() Note that this commit changes availability of C-states on affected platforms. The entries for duty_width and duty_offset are replaced with _PTC entry, if clock throttling in C1 is available. These boards already have definition for _CST and should not be affected: apple/macbook21, dell/e6400, getac/p470, lenovo/t400, lenovo/t60, lenovo/x200, lenovo/x60, roda/rk9 The _CST entry has preference over p_lvl2_lat and p_lvl3_lat fields. The c3_latency entry from static devicetree does not appear in get_cst_entries() implementations in the following boards: apple/macbook21, getac/p470, lenovo/t60 These boards no not have definitions for _CST, therefore C2 and C3 states will be disabled with this commit: acer/g43t-am3, asrock/g41c-gs, asus/p5gc-mx, asus/p5qc, asus/p5ql-em, asus/p5qpl-am, foxconn/d41s, foxconn/g41s-k, gigabyte/ga-945gcm-s2l, gigabyte/ga-d510ud, gigabyte/ga-g41m-es2l, ibase/mb899, intel/d510mo, intel/d945gclf, intel/dg41wv, intel/dg43gt, kontron/986lcd-m, lenovo/thinkcentre_a58, roda/rk886ex Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/speedstep/acpi.c M src/include/cpu/intel/speedstep.h M src/southbridge/intel/i82801gx/fadt.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/fadt.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/fadt.c M src/southbridge/intel/i82801jx/lpc.c 8 files changed, 64 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/74441/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1950ceac7daf8d8e91c74f1090c7451cb92e100 Gerrit-Change-Number: 74441 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit
by Himanshu Sahdev (Code Review) 02 May '23

02 May '23

Attention is currently required from: Subrata Banik, Derek Huang, Andrey Petrov. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74784 ) Change subject: drivers/intel/fsp2_0: Apply FSP Reset Status W/A for MultiPhaseSiInit ...................................................................... Patch Set 5: (1 comment) File src/drivers/intel/fsp2_0/silicon_init.c: https://review.coreboot.org/c/coreboot/+/74784/comment/d4adc5b1_8ca63c1e PS5, Line 199: status = fsp_get_pch_reset_status(); You aren't actually be reading the status from the dedicated HOB if it doesn't exists for some reason (https://review.coreboot.org/c/coreboot/+/74783/5/src/soc/intel/common/fsp_r…) and will lose the last status from multi_phase_si_init as well. Is setting status to 0 is intentional here in case !hob? -- To view, visit https://review.coreboot.org/c/coreboot/+/74784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I749c9986e17e4cbab333b29425c9a4a4ba4128fa Gerrit-Change-Number: 74784 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 02 May 2023 08:49:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: cpu/x86/smm_stub.S: Add a retpoline around the main C handler
by Jan Samek (Code Review) 02 May '23

02 May '23

Attention is currently required from: Nico Huber, Martin L Roth, Subrata Banik, Patrick Rudolph, Benjamin Doron, Julius Werner, Maximilian Brune, Arthur Heymans. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67735 ) Change subject: cpu/x86/smm_stub.S: Add a retpoline around the main C handler ...................................................................... Patch Set 2: (3 comments) File src/cpu/x86/smm/smm_stub.S: https://review.coreboot.org/c/coreboot/+/67735/comment/36d7cda6_4788f61b PS2, Line 256: 2f What are these offsets targeting? https://review.coreboot.org/c/coreboot/+/67735/comment/9cc75400_ba11da68 PS2, Line 268: 1b Ditto. https://review.coreboot.org/c/coreboot/+/67735/comment/b46ed80a_ea0675db PS2, Line 292: mov c_handler, %eax : call *%eax Isn't the retpoline also needed on IA-32? -- To view, visit https://review.coreboot.org/c/coreboot/+/67735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93be3cd6a8c5f1ec29b3bc43195823ac49ec61c5 Gerrit-Change-Number: 67735 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 02 May 2023 08:45:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: atlas testing
by Lean Sheng Tan (Code Review) 02 May '23

02 May '23

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74914 ) Change subject: atlas testing ...................................................................... atlas testing Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Icb7a1e80c2d48835dadb8a2673662cb5bbaa6d7f --- M src/mainboard/prodrive/atlas/devicetree.cb M src/mainboard/prodrive/atlas/romstage_fsp_params.c 2 files changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/74914/1 diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 1c4af58..bcc81a1 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -116,7 +116,7 @@ # without DDT enabled, edk2 doesn't even finish (TODO) device ref dtt on end device ref pcie4_0 on - register "cpu_pcie_rp[CPU_RP(1)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" + register "cpu_pcie_rp[CPU_RP(1)].flags" = "PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED" register "cpu_pcie_rp[CPU_RP(1)].pcie_rp_aspm" = "ASPM_DISABLE" register "cpu_pcie_rp[CPU_RP(1)].PcieRpL1Substates" = "L1_SS_DISABLED" end diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index d460a05..74615e6 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -98,4 +98,8 @@ memupd->FspmConfig.PcieClkSrcClkReq[5] = 0; memupd->FspmConfig.PcieClkSrcUsage[6] = 7; // Rootport 8 memupd->FspmConfig.PcieClkSrcClkReq[6] = 0; + memupd->FspmConfig.PcieClkSrcUsage[7] = 1; // Rootport 2 + memupd->FspmConfig.PcieClkSrcClkReq[7] = 0; + memupd->FspmConfig.PcieClkSrcUsage[8] = 0; // Rootport 1 + memupd->FspmConfig.PcieClkSrcClkReq[8] = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/74914 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7a1e80c2d48835dadb8a2673662cb5bbaa6d7f Gerrit-Change-Number: 74914 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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