coreboot-gerrit May 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Anil Kumar K (Code Review) 03 May '23

03 May '23

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 30: (6 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/e3318415_b2d25398 PS27, Line 156: 0x4 > updated new patchset . […] Done File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/7cdd9fe5_cee06d89 PS30, Line 157: backup PSR command erro > nit: PSR_HECI_FW_DOWNGRADE_BKUP command send failure? Ack https://review.coreboot.org/c/coreboot/+/74577/comment/deb06da3_f27645f2 PS30, Line 776: if (cse_boot_to_rw(cse_bp_info) == CB_SUCCESS) { > Please add a comment like this command requires CSE must boot from RW partition. […] Ack https://review.coreboot.org/c/coreboot/+/74577/comment/199f6704_35a6fa8c PS30, Line 781: return; > This is command send failure case, what is the error recovery path here? Do you want to consider tri […] if command failed we plan to log this as a elog event. There is no need to go to recovery as this is not a catastrophic event . I will push a seperate patch to define new elog event for this purpose. This is WIP https://review.coreboot.org/c/coreboot/+/74577/comment/fde6cdce_1d2c574b PS30, Line 784: Log > Update? Ack https://review.coreboot.org/c/coreboot/+/74577/comment/c2d881fb_94d839da PS30, Line 786: cmos_write(PSR_BACKUP_DONE, PSR_BACKUP_STATUS_CMOS_OFFSET); > It is better we log an event in the event log. we are planning to log failure events in elog as mentioned above -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 30 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 03 May 2023 06:21:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mayan: Enable MXM PCIe slot
by Anand Vaikar (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, ritul guru, Fred Reitberger, Felix Held. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74308 ) Change subject: mb/amd/mayan: Enable MXM PCIe slot ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: Addressed Fred's comments. File src/mainboard/amd/mayan/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74308/comment/dc2c56a3_2d88dfb2 PS3, Line 13: // MXM > This looks like the same change as in CB:74191 - it would probably be better to rebase this patch on […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b Gerrit-Change-Number: 74308 Gerrit-PatchSet: 4 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 May 2023 05:55:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/mayan: Enable MXM PCIe slot
by Anand Vaikar (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, ritul guru, Anand Vaikar, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74308 to look at the new patch set (#4). Change subject: mb/amd/mayan: Enable MXM PCIe slot ...................................................................... mb/amd/mayan: Enable MXM PCIe slot Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/mainboard/amd/mayan/ec.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74308/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/74308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75d7ac488bb005751e6f674ab9a2fd99baad571b Gerrit-Change-Number: 74308 Gerrit-PatchSet: 4 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Himanshu Sahdev (Code Review) 02 May '23

02 May '23

Attention is currently required from: Anil Kumar K, Subrata Banik, Paul Menzel. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 30: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/ee0db5a6_a78e4f7e PS27, Line 150: . > here the length field is the total length excluding the size of header. […] OK https://review.coreboot.org/c/coreboot/+/74577/comment/4aadb000_25b465f6 PS27, Line 156: 0x4 > updated new patchset . […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 30 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 03 May 2023 05:42:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots
by Anand Vaikar (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger, Felix Held. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74069 ) Change subject: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots ...................................................................... Patch Set 6: (3 comments) Patchset: PS6: Addressed Fred's comments. File src/mainboard/amd/mayan/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/74069/comment/18efc2b2_88215c16 PS4, Line 53: // DT > Recommend rebasing on top of CB:74191 (or the other way around) so that both are not doing this same […] Done https://review.coreboot.org/c/coreboot/+/74069/comment/4fb19cdb_ddef2f4c PS4, Line 152: void enable_dt_slot(void) > Make this static and move above `mainboard_get_dxio_ddi_descriptors` and the header change becomes u […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Gerrit-Change-Number: 74069 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 May 2023 05:33:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Sridhar Siricilla (Code Review) 02 May '23

02 May '23

Attention is currently required from: Anil Kumar K, Subrata Banik, Paul Menzel, Himanshu Sahdev. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 30: (7 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/63e83b70_a286b86a PS30, Line 155: heci_send_receive Please do check command prerequisites here? https://review.coreboot.org/c/coreboot/+/74577/comment/7fdd82f9_79c54aa7 PS30, Line 157: backup PSR command erro nit: PSR_HECI_FW_DOWNGRADE_BKUP command send failure? https://review.coreboot.org/c/coreboot/+/74577/comment/c1a8917a_da170fbc PS30, Line 776: if (cse_boot_to_rw(cse_bp_info) == CB_SUCCESS) { Please add a comment like this command requires CSE must boot from RW partition. if CSE boots from RO, there will be GLOBAL RESET, so it is better we log message which tell PSR Back sequence is triggered. This will be helpful decoding CB logs. https://review.coreboot.org/c/coreboot/+/74577/comment/771ecb23_24ccff53 PS30, Line 781: return; This is command send failure case, what is the error recovery path here? Do you want to consider trigger ChromeOS recovery? https://review.coreboot.org/c/coreboot/+/74577/comment/b6b5a08d_c6b4e177 PS30, Line 784: Log Update? https://review.coreboot.org/c/coreboot/+/74577/comment/acb041bd_e8ef1acc PS30, Line 786: cmos_write(PSR_BACKUP_DONE, PSR_BACKUP_STATUS_CMOS_OFFSET); It is better we log an event in the event log. https://review.coreboot.org/c/coreboot/+/74577/comment/a4e0f5c7_e7675416 PS30, Line 788: if (backup_psr_resp.status != PSR_STATUS_SUCCESS) : printk(BIOS_DEBUG, "cse_lite: backup PSR command returned %d\n", : (int)backup_psr_resp.status); Can you handle the condition in the command handler itself? BTW, don't you want to consider retry sending command again if this failure shown? What is the error recovery path here? Do you want to consider trigger ChromeOS recovery? -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 30 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Comment-Date: Wed, 03 May 2023 04:40:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots
by Anand Vaikar (Code Review) 02 May '23

02 May '23

Attention is currently required from: Jason Glenesk, ritul guru, Matt DeVillier, Anand Vaikar, Felix Held. Hello build bot (Jenkins), Jason Glenesk, ritul guru, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74069 to look at the new patch set (#6). Change subject: mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots ...................................................................... mb/amd/mayan:Enable the DT and M.2 SSD1 PCIE slots Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> --- M src/mainboard/amd/mayan/Kconfig M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/mainboard/amd/mayan/ec.c M src/mainboard/amd/mayan/port_descriptors.c 4 files changed, 66 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74069/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/74069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624 Gerrit-Change-Number: 74069 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade
by Sridhar Siricilla (Code Review) 02 May '23

02 May '23

Attention is currently required from: Anil Kumar K, Subrata Banik, Paul Menzel, Himanshu Sahdev. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74577 ) Change subject: soc/intel/cse_lite: Back up PSR data during CSE FW downgrade ...................................................................... Patch Set 30: (2 comments) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/74577/comment/767dc227_0f6ad84a PS29, Line 462: if (cse_data_clear_request(cse_bp_info) != CB_SUCCESS) > yes. during data failure error, we do not care about backing up of the PSR data . Ack File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/74577/comment/f50f1f00_8d9fac7e PS17, Line 84: #define PSR_BACKUP_STATUS_CMOS_OFFSET 161 > i found this by adding prints in cmos_write to check the list of addresses being accessed. […] It is better the CMOS macro definition is moved a dedicated header file cmos.h if there is no such file already.. -- To view, visit https://review.coreboot.org/c/coreboot/+/74577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135d197b5df0a20def823fe615860b5ead4391f8 Gerrit-Change-Number: 74577 Gerrit-PatchSet: 30 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Comment-Date: Wed, 03 May 2023 04:10:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/corsola: Add support for mipi panel
by Yidi Lin (Code Review) 02 May '23

02 May '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74051 ) Change subject: mb/google/corsola: Add support for mipi panel ...................................................................... Patch Set 19: (3 comments) File src/mainboard/google/corsola/display.c: https://review.coreboot.org/c/coreboot/+/74051/comment/17b1f7b5_ad4f53b9 PS19, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ Move bridge related functions to panel_ps8640.c and panel_anx7625. You can take a reference to kukui/panel_{ps8640, anx7625}.c https://review.coreboot.org/c/coreboot/+/74051/comment/d68770da_54ef6050 PS19, Line 245: return get_panel_description(); return NULL if none of boards is matched. File src/mainboard/google/corsola/panel_starmie.c: https://review.coreboot.org/c/coreboot/+/74051/comment/a8060af8_c12c5f9f PS15, Line 13: mainboard_set_regulator_voltage(MTK_ > Done on CB:74341 Oh, I see. If the regulator's voltage is not adjustable, maybe we should implement it in `mainboard_{enable/disable}_regulator` next time. -- To view, visit https://review.coreboot.org/c/coreboot/+/74051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb Gerrit-Change-Number: 74051 Gerrit-PatchSet: 19 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 03 May 2023 04:00:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/dedede/var/boxy: Update devicetree and GPIO table
by Derek Huang (Code Review) 02 May '23

02 May '23

Attention is currently required from: Kevin3 Yang. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74626 ) Change subject: mb/google/dedede/var/boxy: Update devicetree and GPIO table ...................................................................... Patch Set 9: Code-Review+2 (1 comment) Patchset: PS9: > Boxy usb3 port config is same with baseboard devicetree. […] ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Gerrit-Change-Number: 74626 Gerrit-PatchSet: 9 Gerrit-Owner: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Wed, 03 May 2023 03:13:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit May 2023