coreboot-gerrit April 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/purism/librem_cnl: Remove unneeded explicit PNP enable for UART
by Jonathon Hall (Code Review) 12 Apr '23

12 Apr '23

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74362 ) Change subject: mb/purism/librem_cnl: Remove unneeded explicit PNP enable for UART ...................................................................... mb/purism/librem_cnl: Remove unneeded explicit PNP enable for UART Remove explicit PNP 6e.1 configuration for UART. This had no effect, the SuperIO is actually on I/O port 2e. Enabling the 8250IO driver is sufficient to use the UART, the UART device is enabled by default. Test: Build Mini v2 with and without CONFIG_ENABLE_EC_UART1, boot and check output on serial. Change-Id: Idbb39c81cadd633f4718f0682d231dc578d20325 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc D src/mainboard/purism/librem_cnl/variants/librem_mini/com_init.c 2 files changed, 17 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/74362/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc index 59020ef00..20ff438 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc @@ -2,4 +2,3 @@ all-y += die.c smm-y += die.c -bootblock-$(CONFIG_ENABLE_EC_UART1) += com_init.c diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/com_init.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/com_init.c deleted file mode 100644 index 6d0f79f..0000000 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/com_init.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <device/pnp_ops.h> - -#define SERIAL_DEV PNP_DEV(0x6E, 1) /* ITE8528 UART1 */ - -void bootblock_mainboard_early_init(void) -{ - /* Enable the serial port inside the EC */ - pnp_set_logical_device(SERIAL_DEV); - pnp_set_enable(SERIAL_DEV, 1); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/74362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbb39c81cadd633f4718f0682d231dc578d20325 Gerrit-Change-Number: 74362 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mainboard/google/skyrim: Fix MP2 FW naming
by Marshall Dawson (Code Review) 12 Apr '23

12 Apr '23

Marshall Dawson has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74327 ) Change subject: mainboard/google/skyrim: Fix MP2 FW naming ...................................................................... mainboard/google/skyrim: Fix MP2 FW naming Update the blob type for TypeId0x25_Mp2Fw_MDN_AD03.sbin to subprogram 0. Delete the extra MP2FW line. BUG=b:246770914 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I5418b1ed59e1916b971d2eece9f6a2fd0e51b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74327 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/amdfw.cfg 1 file changed, 19 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/amdfw.cfg b/src/mainboard/google/skyrim/amdfw.cfg index 9c83a3f..01e36ab 100644 --- a/src/mainboard/google/skyrim/amdfw.cfg +++ b/src/mainboard/google/skyrim/amdfw.cfg @@ -15,7 +15,6 @@ PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_MDN.sbin PSP_IKEK_FILE TypeId0x21_PspiKek_MDN.bin PSP_SECG0_FILE TypeId0x24_SecPolicy_MDN.sbin -PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_MDN.sbin AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_MDN.sbin PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_MDN.sbin PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin @@ -30,7 +29,7 @@ DMCUB_FILE TypeId0x71_DmcubFw_MDN.sbin PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2_MDN.sbin TA_IKEK_FILE TypeId0x8D_IkekTa_MDN.bin -PSP_MP2FW2_FILE 3rdparty/blobs/mainboard/google/skyrim/TypeId0x25_Mp2Fw_MDN_AD03.sbin +PSP_MP2FW0_FILE 3rdparty/blobs/mainboard/google/skyrim/TypeId0x25_Mp2Fw_MDN_AD03.sbin # BDT PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_MDN_Lpddr5Imem1.csbin -- To view, visit https://review.coreboot.org/c/coreboot/+/74327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5418b1ed59e1916b971d2eece9f6a2fd0e51b1b3 Gerrit-Change-Number: 74327 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Sridhar Siricilla (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Dinesh Gehlot, Paul Menzel, Rizwan Qureshi, Reka Norman. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 30: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 30 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Wed, 12 Apr 2023 16:02:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/corsola: Add detachable Starmie as variant
by Yidi Lin (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Ruihai Zhou. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74048 ) Change subject: mb/google/corsola: Add detachable Starmie as variant ...................................................................... Patch Set 9: (2 comments) File src/mainboard/google/corsola/display.c: https://review.coreboot.org/c/coreboot/+/74048/comment/11a3fe33_747ccb35 PS9, Line 135: const struct edp_bridge *bridge; `const struct edp_bridge *bridge = NULL;` https://review.coreboot.org/c/coreboot/+/74048/comment/9f5a8e5e_42a31895 PS9, Line 153: assert(bridge->power_on); Just return -1 and move to line 145. ``` if (!bridge || !bridge->power_on) return -1; ``` In MIPI panel case, it is possible that we develop on a bare board without the MIPI panel then we will get a NULL handler(CB:74051). We should not assert here and block the booting if the MIPI panel does not exist. -- To view, visit https://review.coreboot.org/c/coreboot/+/74048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Gerrit-Change-Number: 74048 Gerrit-PatchSet: 9 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 16:00:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/meteorlake: Add VPU into the DMAR SATC table
by John Zhao (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74221 ) Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/acpi.c: https://review.coreboot.org/c/coreboot/+/74221/comment/802046b1_dc4faa28 PS1, Line 273: acpi_create_dmar_ds_pci > valid point. The VPU entry should only depend on Vt-d validity along with the IPU. The updated DMAR table has the same scope with MTL BIOS/Windows. If VPU device is not enabled, no impact since the VPU kernel driver will not be loaded. By the way, the MTL iommu kernel driver only has support for Gfx and IPU. VPU would need to be added into iommu in order to support the VPU IO virtualization. I enabled VPU, updated the iommu driver and observed the following message: pci 0000:00:0b.0: DMAR: Passthrough IOMMU for integrated Intel VPU -- To view, visit https://review.coreboot.org/c/coreboot/+/74221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc Gerrit-Change-Number: 74221 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 15:52:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Raul Rangel (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 4: Code-Review+2 (3 comments) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/74334/comment/00b55a29_66054c1d PS4, Line 54: can_use_dma Have you checked if all the new targets we are reading are 64byte aligned? https://review.coreboot.org/c/coreboot/+/74334/comment/d9744c76_1c70300d PS4, Line 228: spi_dma_readat When I took a stab at this, I tried keeping the mmap semantics because the ucode update code would mmap the whole ucode blob, and iterate reading only 4 bytes for each type of ucode. We didn't want to read the whole thing into RAM since that would be a waste. It looks like the ucode update code has been refactored to have individual files, so we no longer need to iterate the ucode blobs. https://source.corp.google.com/chromeos_public/src/third_party/coreboot/src… I'm glad we are getting the SPI dma benefits without the complexity of preload! File src/soc/amd/mendocino/Kconfig: https://review.coreboot.org/c/coreboot/+/74334/comment/e974ff01_e37aa91f PS4, Line 246: SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA We should back port this to guybrush and skyrim :) -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Apr 2023 15:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/ibm: Add 4 SPR sockets server board IBM SBP1
by Patrick Rudolph (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Paul Menzel, David Hendricks, Angel Pons, Shuo Liu, Arthur Heymans, Nill Ge, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73392 ) Change subject: mb/ibm: Add 4 SPR sockets server board IBM SBP1 ...................................................................... Patch Set 11: (2 comments) File src/mainboard/ibm/sbp1/Kconfig: https://review.coreboot.org/c/coreboot/+/73392/comment/0fb83879_d971cefc PS9, Line 31: MAX_SOCKET_UPD > MAX_SOCKET_UPD matches with how the FSP was built. […] Done File src/mainboard/ibm/sbp1/include/spr_sbp1_gpio.h: https://review.coreboot.org/c/coreboot/+/73392/comment/ee5c0824_864bcc54 PS10, Line 8: static const struct pad_config gpio_table[] = { > Add this to a compilation unit rather than a header? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/73392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Gerrit-Change-Number: 73392 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 12 Apr 2023 15:46:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [WIP] NO REVIEW util/autoport: Use regex for log reading
by Maximilian Brune (Code Review) 12 Apr '23

12 Apr '23

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74361 ) Change subject: [WIP] NO REVIEW util/autoport: Use regex for log reading ...................................................................... [WIP] NO REVIEW util/autoport: Use regex for log reading The current implementation doesn't work if there are more than one PCIE domain used by the System, since lspci changes it's output depending on whether or not multiple domains are used. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I3daaa1b08ab93ae2b1ebdeba9f2da9dae39b3301 --- M util/autoport/log_reader.go 1 file changed, 43 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/74361/1 diff --git a/util/autoport/log_reader.go b/util/autoport/log_reader.go index b144804..9d9b768 100644 --- a/util/autoport/log_reader.go +++ b/util/autoport/log_reader.go @@ -135,33 +135,45 @@ scanner := bufio.NewScanner(file) PCIList = []PCIDevData{} - + // [domain] : bus : dev . func desc vendor : device + pcieLine := regexp.MustCompile(`^([0-9]{4,}:){0,1}([0-9a-z][0-9a-z]):([0-1][0-9a-f]).([0-7]) .+ \[([0-9a-z]{4}):([0-9a-z]{4})\]`) + hexLine := regexp.MustCompile(`^[0-9a-z]{2,}:( [0-9a-z])+`) for scanner.Scan() { line := scanner.Text() + matches := pcieLine.FindStringSubmatch(line) switch { - case !(len(line) < 7 || !isXDigit(line[0]) || !isXDigit(line[1]) || line[2] != ':' || !isXDigit(line[3]) || !isXDigit(line[4]) || line[5] != '.' || !isXDigit(line[6])): + case len(matches) == 7: cur := PCIDevData{} - fmt.Sscanf(line, "%x:%x.%x", &cur.Bus, &cur.Dev, &cur.Func) - lc := strings.LastIndex(line, ":") - li := strings.LastIndex(line[0:lc], "[") - if li < 0 { - continue + var b, d, f, di, vi uint64 + if b, err = strconv.ParseUint(matches[2], 16, 8); err != nil { + log.Fatal(err) } - ven := 0 - dev := 0 - fmt.Sscanf(line[li+1:], "%x:%x", &ven, &dev) - cur.PCIDevID = uint16(dev) - cur.PCIVenID = uint16(ven) + if d, err = strconv.ParseUint(matches[3], 16, 8); err != nil { + log.Fatal(err) + } + if f, err = strconv.ParseUint(matches[4], 16, 4); err != nil { + log.Fatal(err) + } + if di,err = strconv.ParseUint(matches[5], 16, 16); err != nil { + log.Fatal(err) + } + if vi,err = strconv.ParseUint(matches[6], 16, 16); err != nil { + log.Fatal(err) + } + cur.Bus = int(b) + cur.Dev = int(d) + cur.Func = int(f) + cur.PCIDevID = uint16(di) + cur.PCIVenID = uint16(vi) + fmt.Printf("%2x:%2x.%1x %4x:%4x\n", cur.Bus, cur.Dev, cur.Func, cur.PCIDevID, cur.PCIVenID) cur.ConfigDump = make([]byte, 0x100, 0x1000) PCIList = append(PCIList, cur) - case len(line) > 7 && isXDigit(line[0]) && line[1] == '0' && line[2] == ':': - start := 0 - fmt.Sscanf(line, "%x:", &start) + case hexLine.MatchString(line): cur := &PCIList[len(PCIList)-1] cur.ConfigDump = l.AssignHexLine(line, cur.ConfigDump) } } - + fmt.Println() if err := scanner.Err(); err != nil { log.Fatal(err) } @@ -271,7 +283,7 @@ } defer codec.Close() pin, err := os.Open(l.InputDirectory + "/pin_hwC" + strconv.Itoa(cardno) + - "D" + strconv.Itoa(codecno)) + "D" + strconv.Itoa(codecno)) if err != nil { continue } -- To view, visit https://review.coreboot.org/c/coreboot/+/74361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3daaa1b08ab93ae2b1ebdeba9f2da9dae39b3301 Gerrit-Change-Number: 74361 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Dinesh Gehlot (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Paul Menzel, Rizwan Qureshi, Reka Norman, Sridhar Siricilla. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74005 ) Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... Patch Set 30: (2 comments) File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/74005/comment/cf57a9ea_6e1626be PS28, Line 1242: fw partition request > I had requested to add "Get Image Firmware Version command" in my earlier comment. Ack File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/74005/comment/235e84c9_b1739c70 PS29, Line 1259: nfo request denied, request during recovery mode > I do agree with you, but given warning doesn't indicate what is denied. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 30 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 12 Apr 2023 15:33:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/cmd/block: Implement an API to get firmware partition details
by Dinesh Gehlot (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Dinesh Gehlot, Paul Menzel, Rizwan Qureshi, Reka Norman. Hello build bot (Jenkins), SRIDHAR SIRICILLA, Subrata Banik, Kangheui Won, Haribalaraman Ramasubramanian, Paul Menzel, Kapil Porwal, Rizwan Qureshi, Reka Norman, Sridhar Siricilla, Meera Ravindranath, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74005 to look at the new patch set (#30). Change subject: soc/intel/cmd/block: Implement an API to get firmware partition details ...................................................................... soc/intel/cmd/block: Implement an API to get firmware partition details This patch retrieves details of a specified firmware partition table. The information retrieved includes the current firmware version and other information about the firmware partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74005/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/74005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Gerrit-Change-Number: 74005 Gerrit-PatchSet: 30 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2023