coreboot-gerrit April 2023

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[M] Change in coreboot[master]: mb/google/brya/var/skolas: Add new GFX devices with custom _PLD
by Won Chung (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli. Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74368 ) Change subject: mb/google/brya/var/skolas: Add new GFX devices with custom _PLD ...................................................................... mb/google/brya/var/skolas: Add new GFX devices with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d --- M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/skolas4es/overridetree.cb 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/74368/1 diff --git a/src/mainboard/google/brya/variants/skolas/overridetree.cb b/src/mainboard/google/brya/variants/skolas/overridetree.cb index d21b3e1..d61b301 100644 --- a/src/mainboard/google/brya/variants/skolas/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas/overridetree.cb @@ -116,6 +116,30 @@ }" device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_custom_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[2].use_custom_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_custom_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + # TCP3 (DP-4) unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf ## sensor information diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb index 5916fc7..b222de4 100644 --- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb @@ -112,6 +112,30 @@ }" device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_custom_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[2].use_custom_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_custom_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + # TCP3 (DP-4) unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf ## sensor information -- To view, visit https://review.coreboot.org/c/coreboot/+/74368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d Gerrit-Change-Number: 74368 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex/var/rex0: Add new GFX devices with custom _PLD
by Won Chung (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74367 ) Change subject: mb/google/rex/var/rex0: Add new GFX devices with custom _PLD ...................................................................... mb/google/rex/var/rex0: Add new GFX devices with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-rex coreboot Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/74367/1 diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 3755227..615e407 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -131,6 +131,28 @@ }" device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD"" + # DDIB for HDMI + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_custom_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) unused + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C1 + register "device[4].name" = ""DD04"" + register "device[4].use_custom_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf device generic 0 alias dptf_policy on end -- To view, visit https://review.coreboot.org/c/coreboot/+/74367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 Gerrit-Change-Number: 74367 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex/var/rex0: Correct _PLD values for USB C0
by Won Chung (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Kapil Porwal. Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74366 ) Change subject: mb/google/rex/var/rex0: Correct _PLD values for USB C0 ...................................................................... mb/google/rex/var/rex0: Correct _PLD values for USB C0 This patch is to denote the correct value of ACPI _PLD for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f --- M src/mainboard/google/rex/variants/rex0/overridetree.cb 1 file changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/74366/1 diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 282c3da..3755227 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -153,7 +153,7 @@ register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi @@ -194,7 +194,7 @@ register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/74366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Gerrit-Change-Number: 74366 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drivers/gfx/generic: Add _PLD support to GFX device
by Won Chung (Code Review) 12 Apr '23

12 Apr '23

Won Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74365 ) Change subject: drivers/gfx/generic: Add _PLD support to GFX device ...................................................................... drivers/gfx/generic: Add _PLD support to GFX device Add _PLD support to GFX device so that each display outputs can store its physical location of connection point. This is to be used primarily for describing DP on USB-C ports in the future patches. BUG=b:277629750 TEST=emerge-${BOARD} coreboot Change-Id: I393207746a9e82c1fd7622ab3661d7b1232cb62f --- M src/drivers/gfx/generic/chip.h M src/drivers/gfx/generic/generic.c 2 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/74365/1 diff --git a/src/drivers/gfx/generic/chip.h b/src/drivers/gfx/generic/chip.h index d600823..dad60602 100644 --- a/src/drivers/gfx/generic/chip.h +++ b/src/drivers/gfx/generic/chip.h @@ -4,6 +4,7 @@ #define __DRIVERS_GFX_GENERIC_CHIP_H__ #include <acpi/acpi_device.h> +#include <acpi/acpi_pld.h> /* Config for electronic privacy screen */ struct drivers_gfx_generic_privacy_screen_config { @@ -35,6 +36,9 @@ unsigned int addr; /* Electronic privacy screen specific config */ struct drivers_gfx_generic_privacy_screen_config privacy; + /* Physical location of connection point */ + bool use_custom_pld; + struct acpi_pld pld; }; /* Config for an ACPI video device defined in Appendix A of the ACPI spec */ @@ -47,7 +51,8 @@ /* The number of output devices defined */ int device_count; /* Config for output devices */ - struct drivers_gfx_generic_device_config device[5]; + /* 1 DDIA + 1 DDIB + 4 TCP */ + struct drivers_gfx_generic_device_config device[6]; }; #endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */ diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 7c6076c..9dac203 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -128,6 +128,10 @@ acpigen_write_name_integer("_STA", 0xF); gfx_fill_privacy_screen_dsm(&config->device[i].privacy); + + if (config->device[i].use_custom_pld) + acpigen_write_pld(&config->device[i].pld); + acpigen_pop_len(); /* Device */ } acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/74365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I393207746a9e82c1fd7622ab3661d7b1232cb62f Gerrit-Change-Number: 74365 Gerrit-PatchSet: 1 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Configure SuperIO for Librem Mini v1/v2
by Jonathon Hall (Code Review) 12 Apr '23

12 Apr '23

Jonathon Hall has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74369 ) Change subject: mb/purism/librem_cnl: Configure SuperIO for Librem Mini v1/v2 ...................................................................... mb/purism/librem_cnl: Configure SuperIO for Librem Mini v1/v2 Configure the SuperIO and logical devices in the device tree. This overrides the power-on default state. UART1 was already enabled, and if ENABLE_EC_UART1 was selected in Kconfig, the LPC UART1 I/O range was also already enabled. The RTC/BRAM interface was enabled (and the BRAM1 base was 0x360 by default), but the LPC I/O range was not opened previously. Now it is open and BRAM bank 1 is accessible. Mouse/Keyboard are not wired to anything on this board and are now disabled. UART2, SMFI, power channel 1, and power channel 2 were enabled previously, but their LPC I/O ranges were not opened and they were not accessible to the OS. Fan control is performed by the EC on this board so there is no change. SWUC and power channels 3-5 were disabled by default, no change. Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/74369/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb index 9270313..cab254a 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb @@ -150,5 +150,29 @@ register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end + device pci 1f.0 on # LPC Bridge + chip superio/ite/it8528e + device pnp 2e.1 on # UART1 + io 0x60 = 0x3F8 + irq 0x70 = 0x04 + end + device pnp 2e.2 off end # UART2 + device pnp 2e.4 off end # System Wake-Up Control (SWUC) + device pnp 2e.5 off end # KBC/Mouse + device pnp 2e.6 off end # KBC/Keyboard + device pnp 2e.a off end # Consumer IR + device pnp 2e.f off end # Shared Memory/Flash Interface (SMFI) + device pnp 2e.10 on # RTC-like Timer + io 0x62 = 0x360 # BRAM1 I/O base address + end + device pnp 2e.11 off end # Power Management I/F Channel 1 (PMC1) + device pnp 2e.12 off end # Power Management I/F Channel 2 (PMC2) + device pnp 2e.13 off end # Serial Peripheral Interface (SSPI) + device pnp 2e.14 off end # Platform Environment Control Interface (PECI) + device pnp 2e.17 off end # Power Management I/F Channel 3 (PMC3) + device pnp 2e.18 off end # Power Management I/F Channel 4 (PMC4) + device pnp 2e.19 off end # Power Management I/F Channel 5 (PMC5) + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/74369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d Gerrit-Change-Number: 74369 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Provide CBFS setting for Mini auto power on
by Jonathon Hall (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Paul Menzel, Angel Pons, Felix Held. Hello build bot (Jenkins), Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74363 to look at the new patch set (#3). Change subject: mb/purism/librem_cnl: Provide CBFS setting for Mini auto power on ...................................................................... mb/purism/librem_cnl: Provide CBFS setting for Mini auto power on Control Mini v1/v2 automatic power on by adding a 'board_settings' file to CBFS. This allows us to use one build each for Mini v1/v2 that is configured differently for different uses. By default, the EC setting is not configured by coreboot, and the OS could configure it. Test: Build Mini v2, boot with no settings in CBFS. Add board_settings configured for automatic power-on, flash, boot, confirm EC now powers on automatically when power applied. Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig.name M src/mainboard/purism/librem_cnl/variants/librem_mini/Makefile.inc A src/mainboard/purism/librem_cnl/variants/librem_mini/mainboard.c 3 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/74363/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Matt DeVillier (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Tim Van Patten, Karthik Ramasubramanian, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Apr 2023 18:37:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA
by Karthik Ramasubramanian (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Martin Roth, Fred Reitberger, Tim Van Patten, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74334 ) Change subject: soc/amd/common/block/lpc/spi_dma: Leverage CBFS_CACHE when using SPI DMA ...................................................................... Patch Set 4: (2 comments) File src/soc/amd/common/block/lpc/spi_dma.c: https://review.coreboot.org/c/coreboot/+/74334/comment/627b9bdd_00491cbc PS4, Line 54: can_use_dma > Have you checked if all the new targets we are reading are 64byte aligned? Atleast the source and dest are 64 byte aligned and the size is > 64 bytes. Copied the log snippet capturing all the files being read. [INFO ] CBFS: Found 'fspm.bin' @0x63c40 size 0x24433 in mcache @0x020250c0 [SPEW ] spi_dma_readat_dma: start: dest: 0x02181600, source: 0x83cc0, size: 148531 -- [INFO ] CBFS: Found 'fallback/ramstage' @0x30300 size 0x2f2d7 in mcache @0x02024fc0 [SPEW ] spi_dma_readat_dma: start: dest: 0x02181600, source: 0x50380, size: 193239 -- [DEBUG] FMAP: area RO_VPD found @ 800000 (16384 bytes) [SPEW ] spi_dma_readat_dma: start: dest: 0x02181600, source: 0x800000, size: 16384 -- [INFO ] CBFS: Found 'fsps.bin' @0x88100 size 0xb357 in mcache @0xb877c300 [SPEW ] spi_dma_readat_dma: start: dest: 0x02187600, source: 0xa8180, size: 45911 -- [INFO ] CBFS: Found 'pci1002,1506.rom' @0x93500 size 0xae00 in mcache @0xb877c380 [SPEW ] spi_dma_readat_dma: start: dest: 0x02187600, source: 0xb3580, size: 44544 -- [INFO ] CBFS: Found 'cpu_microcode_8a00.bin' @0x9e380 size 0xc80 in mcache @0xb877c400 [SPEW ] spi_dma_readat_dma: start: dest: 0x02192400, source: 0xbe400, size: 3200 -- [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x5f680 size 0x4527 in mcache @0xb877c200 [SPEW ] spi_dma_readat_dma: start: dest: 0x02193080, source: 0x7f700, size: 17703 -- [INFO ] Couldn't obtain OEM name from CBI [SPEW ] spi_dma_readat_dma: start: dest: 0x021975c0, source: 0x61e000, size: 4096 -- [INFO ] CBFS: Found 'fallback/payload' @0xc4a80 size 0x2811c in mcache @0xb877c6d8 [SPEW ] spi_dma_readat_dma: start: dest: 0x021985c0, source: 0xe4b00, size: 164124 File src/soc/amd/mendocino/Kconfig: https://review.coreboot.org/c/coreboot/+/74334/comment/5c2c5097_2a1c01dc PS4, Line 246: SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA > We should back port this to guybrush and skyrim :) Ack. On Guybrush, for some reason memory mapped access is better than in skyrim. I am not sure why that is the case. But definitely will backport to both guybrush and skyrim. -- To view, visit https://review.coreboot.org/c/coreboot/+/74334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie30b6324f9977261c60e55ed509e979ef290f1f1 Gerrit-Change-Number: 74334 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Apr 2023 18:16:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Provide CBFS setting for Mini auto power on
by Jonathon Hall (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Paul Menzel, Angel Pons, Felix Held. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74363 ) Change subject: mb/purism/librem_cnl: Provide CBFS setting for Mini auto power on ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/74363/comment/7f740027_fed07825 PS2, Line 9: Control Mini v1/v2 automatic power on by adding a 'board_settings' file : to CBFS. This allows us to use one build each for Mini v1/v2 that is : configured differently for different uses. By default, the EC setting is : not configured by coreboot, and the OS could configure it. : : Add ITE SuperIO configuration to device tree and configure base address : of BRAM1. (BRAM1 contains the EC firmware setting for automatic power : on.) : : Test: Build Mini v2, boot with no settings in CBFS. Add board_settings : configured for automatic power-on, flash, boot, confirm EC now powers : on automatically when power applied. > Please reflow for 72 characters per line. Good catch, did not realize the Gerrit web editor allows 74 chars per line, d'oh Patchset: PS2: > Can the hunk hooking up the Super I/O be separate? (Is there a change in behavior regarding fan cont […] I'll split that up. Shouldn't be any changes but I will double check what was enabled by default, was a while back that I put this together. You could configure this from the OS, I have not tried nvramtool but I have done it manually. We have customers using these as home servers, and they wanted this baked into the firmware so it could be provisioned easily without an extra step and they did not need board-specific stuff in the OS. Maybe this is influenced by expectations from AMI firmware that offers this as a firmware setting. I did not realize CMOS default values could be put in CBFS though, that's a good thought, I'll check that out. Is there any doc on that by chance? File src/mainboard/purism/librem_cnl/variants/librem_mini/mainboard.c: https://review.coreboot.org/c/coreboot/+/74363/comment/21bfb992_a4744a35 PS2, Line 21: uint8_t ec_power_on = 0; > Any reason to limit the size? Why not `unsigned int` or `bool`? […] It's reading a 1-byte field from the board settings file with memcpy. I thought that was simpler than doing the whole dance of casting the data pointer to a struct pointer since there's just the one setting right now, and it is just read once here (no sense memcpying and then extending to an unsigned int). I can go the struct route if you think that would be clearer though. (It can't be a bool because it's a three-valued setting, the default is not to touch the EC setting so you could configure from the OS if you prefer.) -- To view, visit https://review.coreboot.org/c/coreboot/+/74363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Apr 2023 18:06:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/mb/purism/librem_cnl: Enable Librem 14 jack detect with fixed EC
by Jonathon Hall (Code Review) 12 Apr '23

12 Apr '23

Attention is currently required from: Tim Crawford, Jeremy Soller, Paul Menzel, Angel Pons, Felix Held. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74364 ) Change subject: src/mb/purism/librem_cnl: Enable Librem 14 jack detect with fixed EC ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Related, mostly discusses the EC side of this fix: https://puri.sm/posts/meet-my-friend-jack/ -- To view, visit https://review.coreboot.org/c/coreboot/+/74364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a27b1d51e4f6c7c712bcb2823d21692b9c5ce6 Gerrit-Change-Number: 74364 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 12 Apr 2023 17:37:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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