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Change subject: mb/google/myst: Enable PCIe devices in devicetree
......................................................................
Patch Set 36:
(1 comment)
File src/mainboard/google/myst/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/74112/comment/07a60974_2bad86c8
PS36, Line 12: .start_logical_lane = 13,
: .end_logical_lane = 13,
@Felix: I believe the corresponding logical lane is 1 based on the mapping here - https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/he…. Can you please confirm?
Based on that, the logical lane ID should be updated in the rest of the table.
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Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/74221/comment/e9e36f72_69f15b07
PS1, Line 273: acpi_create_dmar_ds_pci
> I sync to ToT(VPU is disabled) and did not observe error with this CL.
thinking out loud, it still doesn't look clean to have disabled device(s) in the ACPI tables.
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Change subject: soc/intel/meteoerlake: set power limits dynamically
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Patch Set 2: Code-Review+2
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Change subject: mb/google/myst: Add eSPI configuration
......................................................................
Patch Set 30: -Code-Review
(1 comment)
File src/mainboard/google/myst/bootblock.c:
https://review.coreboot.org/c/coreboot/+/74110/comment/9c97bc91_07fc6705
PS30, Line 14: }
> looking at the espi_gpio_table, you're using spi1 for espi, so you're missing the espi_switch_to_sp […]
+1. Thanks for catching that.
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Change subject: util/crossgcc: Update GCC from 11.3 to 12.2
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
gcc-13.1 soon
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Change subject: mb/google/rex/var/screebo: Add initial setup for gpio config
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74475/comment/46b365ca_b360ad9a
PS6, Line 7: mb/google/rex: Add initial setup for gpio config
> I mean please use the format we used in chrome project mb/google/rex/var/screebo:
Done
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Hello build bot (Jenkins), YH Lin, Tarun Tuli, Subrata Banik, Kapil Porwal,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/rex/var/screebo: Add initial setup for gpio config
......................................................................
mb/google/rex/var/screebo: Add initial setup for gpio config
add the initial gpio configuration for screebo initial variant
BUG=b:276814951
TEST=emerge-rex coreboot
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7
---
M src/mainboard/google/rex/variants/screebo/gpio.c
1 file changed, 421 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74475/7
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Change subject: mb/google/rex: Add initial setup for gpio config
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74475/comment/fc4d04f9_a8e2cb9c
PS6, Line 7: mb/google/rex: Add initial setup for gpio config
I mean please use the format we used in chrome project mb/google/rex/var/screebo:
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Change subject: util/crossgcc: Update GCC from 11.3 to 12.2
......................................................................
util/crossgcc: Update GCC from 11.3 to 12.2
Change-Id: Ia15e48847c6aea4f3188588b5092250568f16a09
Signed-off-by: Felix Singer <felix.singer(a)secunet.com>
---
M util/crossgcc/buildgcc
D util/crossgcc/patches/gcc-11.3.0_gnat.patch
R util/crossgcc/patches/gcc-12.2.0_ada-musl_workaround.patch
R util/crossgcc/patches/gcc-12.2.0_asan_shadow_offset_callback.patch
A util/crossgcc/patches/gcc-12.2.0_gnat.patch
R util/crossgcc/patches/gcc-12.2.0_libcpp.patch
R util/crossgcc/patches/gcc-12.2.0_libgcc.patch
D util/crossgcc/sum/gcc-11.3.0.tar.xz.cksum
A util/crossgcc/sum/gcc-12.2.0.tar.xz.cksum
9 files changed, 57 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/66922/15
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