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Change subject: mb/google/myst: Configure WLAN
......................................................................
Patch Set 38:
(2 comments)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74113/comment/4c008dc0_ced34fc4
PS38, Line 246: variant_early_override_gpio_table
We have never used the early override gpio table in Skyrim. So can be removed.
https://review.coreboot.org/c/coreboot/+/74113/comment/13c28511_2c393420
PS38, Line 258: variant_romstage_override_gpio_table
Same comment as above.
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74484 )
Change subject: cpu/x86/Kconfig: Disable choice X2APIC_ONLY
......................................................................
cpu/x86/Kconfig: Disable choice X2APIC_ONLY
The choice isn't supported as the code to enable X2APIC mode
accesses X2APIC registers itself before enabling X2APIC mode.
Disable it and add help messages.
The X2APIC mode can still be enabled by a user using the
X2APIC_RUNTIME "Support both XAPIC and X2APIC" Kconfig.
Not only is the enabling broken, but also every register access
using the LAPIC API before MPinit causes a crash.
A possible workaround would be to enable/configure the LAPIC in
bootblock or assembly. As it's unclear which effect it has on
binary blobs this is not done here as possible fix.
Change-Id: I74831efa25c01a44c4994fe8f35131c6e67ba67b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/cpu/x86/Kconfig
1 file changed, 38 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/74484/1
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c85eace..54a48d5 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -50,16 +50,18 @@
config XAPIC_ONLY
prompt "Set XAPIC mode"
bool
-
-config X2APIC_ONLY
- prompt "Set X2APIC mode"
- bool
- depends on PARALLEL_MP
+ help
+ Choose this option to use XAPIC mode in MPinit. In this mode only 255 CPUs
+ are supported.
config X2APIC_RUNTIME
prompt "Support both XAPIC and X2APIC"
bool
depends on PARALLEL_MP
+ help
+ Choose this option to enable X2APIC in MPinit if supported. It X2APIC mode
+ is not supported XAPIC mode will be used. X2APIC mode supports more than 255
+ CPU cores.
config X2APIC_LATE_WORKAROUND
prompt "Use XAPIC for AP bringup, then change to X2APIC"
@@ -74,6 +76,13 @@
endchoice
+config X2APIC_ONLY
+ def_bool n
+ depends on PARALLEL_MP
+ help
+ Set X2APIC mode. This is not supported as the code enabling X2APIC mode
+ currently accesses registers before enabling them and crashes.
+
config UDELAY_LAPIC
bool
default n
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Change subject: mb/google/rex/var/screebo: Add initial setup for gpio config
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Patchset:
PS7:
I don't kw the location of Screebo schematics or platform mapping doc to review this cl
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Change subject: soc/intel/meteoerlake: set power limits dynamically
......................................................................
Patch Set 2:
(5 comments)
File src/soc/intel/meteorlake/chip.h:
https://review.coreboot.org/c/coreboot/+/74380/comment/7b76bc16_a043c8f4
PS2, Line 33: static const struct
wondering if u have more consumers of this data structure beyond systemagent.c file ?
File src/soc/intel/meteorlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/74380/comment/8cf761c4_793a02ab
PS2, Line 152: soc_systemagent_init
i would have refactored this code as below
```
void soc_systemagent_init(struct device *dev)
{
/* Enable Power Aware Interrupt Routing */
enable_power_aware_intr();
/* Configure TDP */
configure_tdp(dev);
}
```
inside configure_tdp:
```
void configure_tdp(struct device *dev)
{
struct device *sa;
/* Get System Agent PCI ID */
sa = pcidev_path_on_root(PCI_DEVFN_ROOT);
sa_pci_id = sa ? pci_read_config16(sa, PCI_DEVICE_ID) : 0xFFFF;
if (sa_pci_id == 0xFFFF) {
printk(BIOS_WARNING, "Unknown SA PCI Device!\n");
return;
}
...
}
```
https://review.coreboot.org/c/coreboot/+/74380/comment/783c11a7_71d13647
PS2, Line 168: 0xFFFF
shouldn't we skip the below operations if ID is 0xFFFF? what is the point of running into the `for` loop when id itself is not valid?
https://review.coreboot.org/c/coreboot/+/74380/comment/54326f5f_760745b8
PS2, Line 183: if (i == ARRAY_SIZE(cpuid_to_mtl)) {
can u use a bool to know if config_tdp is successful ?
https://review.coreboot.org/c/coreboot/+/74380/comment/93a001c7_7c9bc8ef
PS2, Line 188: printk(BIOS_DEBUG, "Configured power limits for SA ID: 0x%4x\n", sa_pci_id);
please move this line into line#178 to avoid a else case here.
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Change subject: mb/google/brya/var/constitution: Generate SPD ID for supported parts
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74497/comment/6c1c4cfd_8443fb42
PS1, Line 13: 267539938
> b:267539938
done.
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Hello David Wu, Tarun Tuli, Nick Vaccaro, Matthew Ziegelbaum, Pablo Ceballos, Eric Lai, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74497
to look at the new patch set (#2).
Change subject: mb/google/brya/var/constitution: Generate SPD ID for supported parts
......................................................................
mb/google/brya/var/constitution: Generate SPD ID for supported parts
Add supported memory part in mem_parts_used.txt, then generate.
K4UBE3D4AB-MGCL
BUG=b:267539938
TEST=util/abuild/abuild -p none -t google/brya -x -a
Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d
Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/constitution/memory/Makefile.inc
M src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt
3 files changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/74497/2
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Change subject: mb/google/brya/var/constitution: Generate SPD ID for supported parts
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74497/comment/937aaae6_c85fae6d
PS1, Line 13: 267539938
b:267539938
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Change subject: mb/google/brya/var/constitution: Generate SPD ID for supported parts
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/meteorlake: Add VPU into the DMAR SATC table
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/acpi.c:
https://review.coreboot.org/c/coreboot/+/74221/comment/d3100a81_d7e45864
PS1, Line 273: acpi_create_dmar_ds_pci
> thinking out loud, it still doesn't look clean to have disabled device(s) in the ACPI tables.
+2
These are the onboard devices hence, should be adding device check prior adding into the ACPI table.
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