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Change subject: SMBIOS: Move identification strings
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74452/comment/d0f28a6c_e6e213c9
PS3, Line 9: This improve ccache hit rate
> is there a better argument to be made for moving […]
The motivation was to split these strings away from build/config.h to build/board_id.h, which will only be an input for lib/identity.c. I am still experimenting with ccache to see if I am able to transform hits from "preprocessor hit" to "direct hit", latter is typically much faster and may result with smaller memory footprint.
I have not inspected the binaries that closely yet to check if constant Kconfig strings currently appear twice expanded in the binaries. Output of "objdump -r -d" may actually appear nicer since the references are to symbolic names found in source.
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Change subject: configs/config.amd_mayan: Add defconfig file for Mayan board
......................................................................
Abandoned
Abandoning this PR, as we will share the config file to customer directly.
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Change subject: cpu/x86/Kconfig: Disable choice X2APIC_ONLY
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Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74484/comment/f7bb2e81_eb1959d1
PS1, Line 10: accesses X2APIC registers itself before enabling X2APIC mode.
Did you bisect which commit changed this?
We have both initial_lapicid() from CPUID and lapicid() from LAPIC. Might be a matter of simply changing one of those instances to keep supporting X2APIC_ONLY.
https://review.coreboot.org/c/coreboot/+/74484/comment/d8052870_a1ba2eda
PS1, Line 17: using the LAPIC API before MPinit causes a crash.
One should not have placed any LAPIC register accesses prior to enable_lapic() in the first place? One should not assume LAPIC is enabled at default address on reset, so in theory XAPIC register access is equally done too early.
File src/cpu/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/74484/comment/48da2119_34827dfb
PS1, Line 55: are supported.
With this option, if CPU has X2APIC support, OS may make the switch.
This again means, one cannot make lapicid() call inside SMM, as LAPIC MMIO access is then disabled. So if we are not willing to keep track of proper call-sites for LAPIC register accesses, XAPIC_ONLY should only be the default for platforms with no X2APIC support in silicon.
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Change subject: util: Use common ARRAY_SIZE define
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Set Ready For Review
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Change subject: mb/google/kukui: Add sdram configs for RAM code 0x33 and 0x34
......................................................................
Patch Set 6: Code-Review+2
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73469/comment/fd156543_3ee3d5dc
PS5, Line 7: Samsung K3UBE3D4AB-MGCL 4GB and
: Hynix H54G68CYRBX248 8GB support for Pico
> thanks, done.
Ack
https://review.coreboot.org/c/coreboot/+/73469/comment/e669655b_c1c58714
PS5, Line 10: Add new RAM ID 0x33 and 0x34 for new memory support
: leverage sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for K4UBE3D4AB-MGCL 4GB
: and sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for H54G68CYRBX248 8GB
> thanks, done.
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/73469/comment/69df7777_435839ba
PS6, Line 10:
Line break here.
https://review.coreboot.org/c/coreboot/+/73469/comment/b8e1c226_9b537db7
PS6, Line 11:
Line break here.
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Change subject: mb/google/kukui: Add sdram configs for RAM code 0x33 and 0x34
......................................................................
Patch Set 6: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/73469/comment/717ff478_8657f9ce
PS5, Line 7: Samsung K3UBE3D4AB-MGCL 4GB and
: Hynix H54G68CYRBX248 8GB support for Pico
> sdram configs for RAM code 0x33 and 0x34
thanks, done.
https://review.coreboot.org/c/coreboot/+/73469/comment/6e376dfd_2a9641c3
PS5, Line 10: Add new RAM ID 0x33 and 0x34 for new memory support
: leverage sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for K4UBE3D4AB-MGCL 4GB
: and sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for H54G68CYRBX248 8GB
> ``` […]
thanks, done.
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