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Subrata Banik has uploaded a new patch set (#22) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74208 )
Change subject: soc/intel/cmn/cse: Store ISH firmware version into CBMEM
......................................................................
soc/intel/cmn/cse: Store ISH firmware version into CBMEM
The patch stores the ISH in the CBMEM table. It verifies CSE has been
updated by comparing previous and current CSE versions. If it has, the
patch updates the previous CSE version with the current CSE version. It
then updates the CBMEM table with the current ISH version.
BUG=b:273661726
TEST=The current and old CSE and ISH versions are verified on the
google/nissa during cold and warm reboots.
Additionally, version updates are verified by a debug patch that
purposely updated the stored cse version.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 75 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/74208/22
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Attention is currently required from: Tarun Tuli, Subrata Banik, Dinesh Gehlot, Arthur Heymans.
Subrata Banik has uploaded a new patch set (#18) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/74256 )
Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
......................................................................
{commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called from RAMSTAGE based on boot state
machine depending upon CSE sync config options
(`SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE` or
`SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE`).
Additionally, this patch adds a configuration option,
'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage
of firmware version information in CBMEM memory. This information can be
used to identify the firmware version that is currently installed on the
system. The option depends on the `DRIVERS_INTEL_ISH` config and
platform should be flexible enough to opt out from enabling this
feature.
The cost of sending HECI command to read the CSE FPT is significant
(~200ms) hence, the idea is to read the CSE RW version on every cold
reset (to cover the CSE update scenarios) and store into CBMEM to
avoid the cost of resending the HECI command in all consecutive warm
boots.
Later boot stages can just read the CBMEM ID to retrieve the ISH
version if required.
Finally, ensure this feature is platform specific hence, getting
enabled for the platform that would like to store the ISH version into
the CBMEM and parse to perform some additional work.
BUG=b:273661726
TEST=Able to build and boot google/marasov.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
4 files changed, 138 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/74256/18
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74256 )
Change subject: {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
......................................................................
Patch Set 17: Code-Review+2
(1 comment)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/74256/comment/5429f4af_23a50a66
PS16, Line 1250: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && !s3wake) {
: timestamp_add_now(TS_CSE_FW_SYNC_START);
: cse_fw_sync();
: timestamp_add_now(TS_CSE_FW_SYNC_END);
:
: if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION))
: store_cse_rw_fw_version();
: }
: }
> > > > > The codeflow is quite confusing... […]
Otherway this can be done by just checking the CSE Lite version in the CSE RW blob's metadata. In this scenario, coreboot need not interact with CSE and checking CSE blob only once is required. We plan to add the change later one this patchtrain get merged.
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Change subject: mb/amd/birman: Update DXIO descriptors per schematic
......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15:
would be good to set up the wlan/wwan dxio descriptors so that they match what's selected in the wlan/wwan kconfig options introduced in the ec patch
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Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74430/comment/f98811a7_9fea9390
PS3, Line 12:
> not sure if i missed a patch in the series, but src/southbridge/intel/i82801[d,g,i,j]x/fadt. […]
Well there are CB:74439 CB:74440 CB:74441
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Change subject: mb/google/myst: Store XHCI PCI resources
......................................................................
Patch Set 13: Code-Review+2
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Change subject: soc/amd/phoenix: Update XHCI events
......................................................................
Patch Set 13: Code-Review+2
(1 comment)
File src/soc/amd/phoenix/xhci.c:
https://review.coreboot.org/c/coreboot/+/74280/comment/5af85d64_9b3a31e9
PS13, Line 3: /* TODO: Update for Phoenix */
Not for this change.
@Felix, Can you please help update this table. There are supposed to be 4 XHCI controllers and only 2 of them under GPP Bridge A are configured in the table.
We also need to update the table to include XHCI controllers downstream of GPP Bridge C.
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Change subject: mb/google/myst: Configure WLAN
......................................................................
Patch Set 39: Code-Review+2
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Change subject: mb/google/myst: Enable gfx_hda
......................................................................
Patch Set 12: Code-Review+2
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Change subject: mb/google/myst: Enable mp2 device
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