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Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
mb/google/skyrim: Fix eMMC reset GPIO
On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6).
Update the port_descriptors to link the correct reset GPIO. Data
is from the skyrim variant schematics and go/skyrim-gpios.
BUG=b:278759559
TEST=None
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79
---
M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
2 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74512/3
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Attention is currently required from: Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer.
Hello Jason Nien, Martin Roth, Tim Van Patten, Karthik Ramasubramanian, Mark Hasemeyer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74512
to look at the new patch set (#2).
Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
mb/google/skyrim: Fix eMMC reset GPIO
On Whiterun, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6).
Update the port_descriptor to link the correct reset GPIO. Data
is from the Whiterun schematic and go/skyrim-gpios.
BUG=b:278759559
TEST=None
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79
---
M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
2 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/74512/2
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Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74512 )
Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74512/comment/71a209d0_341a9710
PS1, Line 9: On Whiterun, the eMMC reset GPIO should be SSD_AUX_RST_L(GPIO6).
> Skyrim, frostflow and crystaldrift use the right GPIO. Markarth needs to be updated.
Done
https://review.coreboot.org/c/coreboot/+/74512/comment/307660fe_68563cd8
PS1, Line 9: SSD_AUX_RST_L(GPIO6)
> nit: add a space: `SSD_AUX_RST_L (GPIO6)`
Done
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Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74512/comment/7ef731f8_cf8103a8
PS1, Line 9: On Whiterun, the eMMC reset GPIO should be SSD_AUX_RST_L(GPIO6).
> It looks like everything should be updated to GPIO6. […]
Skyrim, frostflow and crystaldrift use the right GPIO. Markarth needs to be updated.
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Change subject: mb/amd/birman/ec.c: Update EC configuration
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/amd/birman/Kconfig:
https://review.coreboot.org/c/coreboot/+/73971/comment/6e948ada_b06f5122
PS10, Line 120: WWAN
wlan
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Change subject: mb/google/skyrim: Fix eMMC reset GPIO
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74512/comment/492cb62e_c6a2ea22
PS1, Line 9: On Whiterun, the eMMC reset GPIO should be SSD_AUX_RST_L(GPIO6).
It looks like everything should be updated to GPIO6.
Will there be other CLs for the other boards?
https://review.coreboot.org/c/coreboot/+/74512/comment/a021caa5_92cd1dd7
PS1, Line 9: SSD_AUX_RST_L(GPIO6)
nit: add a space: `SSD_AUX_RST_L (GPIO6)`
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Change subject: mb/starlabs/starbook: Add ramtop_cmos_offset
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/starlabs/starbook/cmos.layout:
https://review.coreboot.org/c/coreboot/+/74432/comment/5feb6a32_2bc403fe
PS2, Line 42: 800
> Seems good now, at least according to my theory. […]
Your theory seemed accurate, cmos was corrupt if not reset. After this, no problems (so far!)
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Change subject: mb/starlabs/starbook: Add ramtop_cmos_offset
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/mainboard/starlabs/starbook/cmos.layout:
https://review.coreboot.org/c/coreboot/+/74432/comment/9b06e640_80be1494
PS2, Line 42: 800
> The ramstop feature doesn't seem to use the option table API and I don't see […]
Seems good now, at least according to my theory. But please share your test results :)
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Change subject: soc/intel/common: Make ramtop offset configurable
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/basecode/ramtop/ramtop.c:
https://review.coreboot.org/c/coreboot/+/74511/comment/197cecb6_1bd9ecb8
PS2, Line 23: CMOS_VSTART_ramtop_cmos_offset
If there is no other code to sync with, I think we can just use
CMOS_VSTART_ramtop_cmos_offset w/o comparing it to anything redundant,
and fall back to the default value if no option table is used.
Something like
#if CONFIG(USE_OPTION_TABLE)
#include "option_table.h"
#if CMOS_VSTART_ramtop_cmos_offset % 8 == 0
#define RAMTOP_CMOS_OFFSET (CMOS_VSTART_ramtop_cmos_offset / 8)
#else
#error ...
#endif
...
#else
#define RAMTOP_CMOS_OFFSET 100
#endif
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